Alternatives and similar repositories for blue-udp

Users that are interested in blue-udp are comparing it to the libraries listed below

• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆102Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• datenlord / blue-rdma
  RoCEv2 hardware implementation in Bluespec SystemVerilog
  ☆27Updated 10 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆72Updated 10 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆28Updated last year
• antmicro / verilator-verification-features-tests
  ☆27Updated this week
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 6 months ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last week
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 3 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated 3 weeks ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated last week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆58Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆79Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆65Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆46Updated 9 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆48Updated 4 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆41Updated last month