taneroksuz / rv-diiosLinks
6-stage dual-issue in-order superscalar risc-v cpu with floating point unit
☆14Updated 3 weeks ago
Alternatives and similar repositories for rv-diios
Users that are interested in rv-diios are comparing it to the libraries listed below
Sorting:
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Platform Level Interrupt Controller☆43Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 10 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- To design test bench of the APB protocol☆18Updated 4 years ago
- A Verilog implementation of a processor cache.☆31Updated 7 years ago
- RISC-V Nox core☆68Updated 3 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 10 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆115Updated last year
- ☆13Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆122Updated last month
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆32Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated last year
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- A simple DDR3 memory controller☆60Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆100Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- ☆43Updated 3 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago