A simple implementation of a UART modem in Verilog.
☆175Nov 10, 2021Updated 4 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below
Sorting:
- Simple 8-bit UART realization on Verilog HDL.☆115Apr 27, 2024Updated last year
- Verilog UART☆192Jun 4, 2013Updated 12 years ago
- UART implementation using verilog☆33Feb 14, 2023Updated 3 years ago
- Verilog UART☆536Feb 27, 2025Updated last year
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆40Oct 3, 2025Updated 4 months ago
- A simple, basic, formally verified UART controller☆326Jan 29, 2024Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆300Sep 14, 2023Updated 2 years ago
- Verilog implementation of a RISC-V core☆136Oct 11, 2018Updated 7 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆35Mar 25, 2020Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Dec 7, 2020Updated 5 years ago
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Basic RISC-V Test SoC☆175Apr 7, 2019Updated 6 years ago
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- ☆17Oct 6, 2023Updated 2 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 6 years ago
- SPI Master for FPGA - VHDL and Verilog☆328Aug 22, 2023Updated 2 years ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Aug 16, 2021Updated 4 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- SPI通信实现FLASH读写☆16Mar 18, 2020Updated 5 years ago
- APB master and slave developed in RTL.☆22Oct 25, 2025Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆136Oct 2, 2025Updated 4 months ago
- AMBA bus lecture material☆512Jan 21, 2020Updated 6 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆120Dec 17, 2023Updated 2 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆60Jan 28, 2025Updated last year
- ARM中通过APB总线连接的UART模块☆71Feb 21, 2020Updated 6 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Oct 21, 2016Updated 9 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆356Oct 18, 2025Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Jan 31, 2022Updated 4 years ago
- Gaussian noise generator Verilog IP core☆32May 22, 2023Updated 2 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆32Sep 24, 2018Updated 7 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆569Oct 10, 2021Updated 4 years ago
- RISC-V RV32IMAFC Core for MCU☆42Feb 1, 2025Updated last year
- Generic Register Interface (contains various adapters)☆136Updated this week
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 5 years ago