A simple implementation of a UART modem in Verilog.
☆183Nov 10, 2021Updated 4 years ago
Alternatives and similar repositories for uart
Users that are interested in uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple 8-bit UART realization on Verilog HDL.☆119Apr 27, 2024Updated 2 years ago
- Verilog UART☆197Jun 4, 2013Updated 12 years ago
- UART implementation using verilog☆37Feb 14, 2023Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Verilog UART☆562Feb 27, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆41Oct 3, 2025Updated 7 months ago
- A simple, basic, formally verified UART controller☆338Jan 29, 2024Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 6 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Verilog implementation of a RISC-V core☆139Oct 11, 2018Updated 7 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Various HDL (Verilog) IP Cores☆902Jul 1, 2021Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Nov 22, 2019Updated 6 years ago
- SPI Master for FPGA - VHDL and Verilog☆340Aug 22, 2023Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆327Sep 14, 2023Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆78Dec 7, 2020Updated 5 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Basic RISC-V Test SoC☆193Apr 7, 2019Updated 7 years ago
- ARM中通过APB总线连接的UART模块☆71Feb 21, 2020Updated 6 years ago
- Interface Protocol in Verilog☆51Aug 2, 2019Updated 6 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆28Mar 21, 2022Updated 4 years ago
- AMBA bus lecture material☆533Jan 21, 2020Updated 6 years ago
- APB master and slave developed in RTL.☆24Oct 25, 2025Updated 6 months ago
- Present Crypto Engine in Verilog☆12Feb 27, 2016Updated 10 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆50Oct 21, 2016Updated 9 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆127Dec 17, 2023Updated 2 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 13 years ago
- 32-bit Superscalar RISC-V CPU☆1,247Sep 18, 2021Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆146Oct 2, 2025Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆50Jan 31, 2022Updated 4 years ago
- Implementation of Sobel Filter in Verilog☆27Mar 10, 2017Updated 9 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year