Alternatives and similar repositories for uart

Users that are interested in uart are comparing it to the libraries listed below

• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆106Updated last year
• jamieiles / uart
  Verilog UART
  ☆172Updated 12 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆129Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆149Updated 3 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆353Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆96Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆118Updated 6 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆347Updated last week
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆479Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆267Updated last year
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆138Updated 9 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated this week
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆178Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 7 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆97Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 5 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆85Updated 6 years ago