ben-marshall / uart

Related projects ⓘ

Alternatives and complementary repositories for uart

• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆81Updated 6 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• jamieiles / uart
  Verilog UART
  ☆121Updated 11 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆217Updated this week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆103Updated 6 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆108Updated 2 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆128Updated 8 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆123Updated 5 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆158Updated 2 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆84Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆100Updated last month
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆86Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆140Updated this week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆148Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆199Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆138Updated last year
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆82Updated 6 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆109Updated 10 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year