Wren6991 / Hazard5Links
5-stage RISC-V CPU, originally developed for RISCBoy
☆31Updated 2 years ago
Alternatives and similar repositories for Hazard5
Users that are interested in Hazard5 are comparing it to the libraries listed below
Sorting:
- Reusable Verilog 2005 components for FPGA designs☆45Updated 5 months ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 2 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆98Updated last year
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆56Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- A very simple RISC-V ISA emulator.☆38Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Doom classic port to lightweight RISC‑V☆94Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Tools for FPGA development.☆47Updated 3 weeks ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆56Updated last year
- simple wishbone client to read buttons and write leds☆18Updated last year
- Another tiny RISC-V implementation☆56Updated 4 years ago
- HDMI core in Chisel HDL☆51Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Exploring gate level simulation☆58Updated 3 months ago
- Miscellaneous ULX3S examples (advanced)☆78Updated last month
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- Portable HyperRAM controller☆56Updated 7 months ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Spen's Official OpenOCD Mirror☆50Updated 4 months ago