Alternatives and similar repositories for kasirga_gok_2023

Users that are interested in kasirga_gok_2023 are comparing it to the libraries listed below

• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆12Updated 9 months ago
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆21Updated 2 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆143Updated last week
• kirbyydoge / kasirga_2023
  Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
  ☆12Updated last year
• koraykarakurt / FPGA-from-Zero-to-Hero
  Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
  ☆33Updated last month
• arunkpv / vsd-hdp
  ☆17Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆88Updated last year
• efabless / chipcraft---mest-course
  ☆33Updated 4 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆149Updated 8 months ago
• ARC-Lab-UF / intel-training-modules
  ☆42Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆68Updated last year
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 2 years ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆18Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆46Updated 10 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆57Updated 2 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆56Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• vsdip / vsdfpga_labs
  ☆12Updated last month
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆102Updated 9 months ago
• hughbyrne10 / 100daysofRTL
  100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…
  ☆27Updated 2 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆127Updated 9 months ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆59Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆59Updated last year
• eminfedar / fedar-f1-rv64im
  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
  ☆204Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆91Updated 3 weeks ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆32Updated 3 years ago