RClabiisc / I2SRV64-SS-v1
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆22Updated 6 months ago
Alternatives and similar repositories for I2SRV64-SS-v1:
Users that are interested in I2SRV64-SS-v1 are comparing it to the libraries listed below
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- ☆16Updated last year
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆10Updated 9 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 2 weeks ago
- ☆40Updated 2 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆10Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- ☆11Updated last week
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆21Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆35Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆12Updated 8 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆40Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated 6 months ago
- ☆11Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- ☆13Updated 2 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last month
- RISC-V Nox core☆62Updated 5 months ago
- APB UVC ported to Verilator☆11Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆32Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago