RClabiisc / I2SRV64-SS-v1
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆22Updated 7 months ago
Alternatives and similar repositories for I2SRV64-SS-v1:
Users that are interested in I2SRV64-SS-v1 are comparing it to the libraries listed below
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆37Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆17Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Complete tutorial code.☆16Updated 9 months ago
- ☆40Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last month
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆10Updated this week
- ☆27Updated 10 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated 7 months ago
- ☆12Updated 7 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- Open source ISS and logic RISC-V 32 bit project☆42Updated 2 months ago
- ☆12Updated this week
- Platform Level Interrupt Controller☆36Updated 9 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- ☆16Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- ☆24Updated 3 weeks ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆28Updated last year
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- A compact, configurable RISC-V core☆11Updated 3 weeks ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆10Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- APB UVC ported to Verilator☆11Updated last year