RClabiisc / I2SRV64-SS-v1
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆23Updated 10 months ago
Alternatives and similar repositories for I2SRV64-SS-v1:
Users that are interested in I2SRV64-SS-v1 are comparing it to the libraries listed below
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆40Updated 3 years ago
- ☆17Updated 2 years ago
- Complete tutorial code.☆19Updated last year
- ☆12Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 4 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 10 months ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆31Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 5 months ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆11Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated last week
- Platform Level Interrupt Controller☆40Updated 11 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- RISC-V Nox core☆62Updated last month
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆12Updated 2 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- ☆28Updated last year
- APB UVC ported to Verilator☆11Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 5 months ago
- ☆38Updated last year
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 2 weeks ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago