A small and simple rv32i core written in Verilog
☆18Jul 29, 2022Updated 3 years ago
Alternatives and similar repositories for kleine-riscv
Users that are interested in kleine-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆23Aug 2, 2021Updated 4 years ago
- Controller module for RISC-V core CI/CD☆18Jul 13, 2026Updated 2 weeks ago
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Jul 12, 2024Updated 2 years ago
- Submission template for Tiny Tapeout 7 - Verilog HDL Projects☆22May 30, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- ☆18Jul 9, 2026Updated 2 weeks ago
- ☆14Sep 27, 2022Updated 3 years ago
- ☆13Jan 14, 2021Updated 5 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Custom ASIC Design for SHA-256☆14Nov 22, 2025Updated 8 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆132Dec 17, 2023Updated 2 years ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆26May 22, 2022Updated 4 years ago
- Running COBOL on the wild!? No OS required, works with multiboot☆11Jul 31, 2023Updated 2 years ago
- AXI Verification using UVM Testbench☆16Oct 20, 2024Updated last year
- A modular, Lua-based operating system project.☆18Aug 21, 2010Updated 15 years ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated 11 months ago
- Simple RiscV core for academic purpose.☆22Apr 29, 2020Updated 6 years ago
- TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples☆72Nov 1, 2023Updated 2 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14May 26, 2026Updated 2 months ago
- ☆101Jun 24, 2025Updated last year
- yolog.dev releases, feedback & support☆16Feb 2, 2026Updated 5 months ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- A VM that uses LFSR instead of a normal program counter that runs Forth☆17Apr 14, 2026Updated 3 months ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 8 months ago
- SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent☆27Jul 10, 2018Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- STLink library with WebUSB☆12Jan 2, 2022Updated 4 years ago
- RISC-V processor model☆11Nov 10, 2020Updated 5 years ago
- Convert Verilog to a Hardcaml design☆22Jul 10, 2026Updated 2 weeks ago
- Processor CI project Website☆10Jul 9, 2026Updated 2 weeks ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- verilog core for ws2812 leds☆35Nov 3, 2021Updated 4 years ago