rolandbernard / kleine-riscvLinks
A small and simple rv32i core written in Verilog
☆17Updated 3 years ago
Alternatives and similar repositories for kleine-riscv
Users that are interested in kleine-riscv are comparing it to the libraries listed below
Sorting:
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆67Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated 3 weeks ago
- ☆20Updated 8 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 7 months ago
- ☆27Updated 6 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Implementation of a RISC-V CPU in Verilog.☆17Updated 10 months ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems an…☆15Updated 5 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Updated 4 years ago
- RV32I single cycle simulation on open-source software Logisim.☆21Updated 3 years ago
- GUI editor for hardware description designs☆30Updated 2 years ago
- Mini CPU design with JTAG UART support☆21Updated 4 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆20Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- Tools for FPGA development.☆49Updated 5 months ago
- Python script for controlling the debug-jtag port of riscv cores☆15Updated 4 years ago
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- simple wishbone client to read buttons and write leds☆19Updated 2 years ago
- PCB combining Raspberry Pi Pico and iCE40 FPGA☆31Updated last year
- Another tiny RISC-V implementation☆64Updated 4 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- Optimized RISC-V FP emulation for 32-bit processors☆36Updated 4 years ago
- Quite OK image compression Verilog implementation☆23Updated last year