kirbyydoge / kasirga_2023Links
Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
☆14Updated 2 years ago
Alternatives and similar repositories for kasirga_2023
Users that are interested in kasirga_2023 are comparing it to the libraries listed below
Sorting:
- Matrak Verilog ile yazılmış bir RISC-V işlemcidir.☆11Updated last year
- 64-bit RISC-V processor☆16Updated 3 years ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆21Updated 2 years ago
- KASIRGA - GUN | RV32IMCX☆11Updated last year
- Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı☆19Updated 2 years ago
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆213Updated 4 years ago
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆20Updated 3 years ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆36Updated 6 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆131Updated 10 years ago
- SystemVerilog Tutorial☆190Updated 2 months ago
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆15Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆164Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆19Updated 2 years ago
- "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.☆113Updated last year
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆290Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…☆15Updated 6 months ago
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆27Updated 2 years ago
- 5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.☆24Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆133Updated 2 years ago
- Implementation of RISC-V RV32I☆28Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆175Updated 2 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆153Updated 3 months ago
- 100 Days of RTL☆406Updated last year
- Verilog HDL files☆170Updated last year
- https://caravel-user-project.readthedocs.io☆227Updated 11 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆32Updated last year
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆71Updated 4 years ago
- An inhouse RISC-V 32-bits CPU☆18Updated 7 months ago