kirbyydoge / kasirga_2023
Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
☆12Updated last year
Related projects ⓘ
Alternatives and complementary repositories for kasirga_2023
- KASIRGA-GUN | RV32IMCX☆12Updated 2 months ago
- Single Cycle RISC MIPS Processor☆30Updated 3 years ago
- 64-bit RISC-V processor☆12Updated last year
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆15Updated last year
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆19Updated last year
- Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı☆14Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆67Updated 10 months ago
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆186Updated 3 years ago
- SystemVerilog Tutorial☆113Updated 11 months ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆53Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆52Updated last week
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- ☆9Updated 4 months ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆12Updated 11 months ago
- Lecture about FIR filter on an FPGA☆13Updated 5 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆93Updated 9 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆16Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆110Updated 3 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆14Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆44Updated last month
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆21Updated 3 years ago
- "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.☆96Updated 4 months ago
- ☆13Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆48Updated 2 years ago
- RISC-V Embedded Processor for Approximate Computing☆118Updated last week
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆205Updated 3 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆46Updated 9 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year