Alternatives and similar repositories for kasirga_2023

Users that are interested in kasirga_2023 are comparing it to the libraries listed below

• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆17Updated 2 years ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆11Updated last year
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• eminfedar / fedar-f1-rv64im
  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
  ☆211Updated 4 years ago
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 2 years ago
• mbaykenar / mpw7_yonga_soc
  Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C
  ☆18Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆13Updated last week
• FPGADude / Digital-Design
  Verilog HDL files
  ☆155Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆178Updated last week
• necaticakaci / matrak
  Matrak Verilog ile yazılmış bir RISC-V işlemcidir.
  ☆11Updated last year
• SRA-VJTI / synapse32
  An inhouse RISC-V 32-bits CPU
  ☆18Updated 4 months ago
• luccas641 / DE2-115-SDRAM-Controller
  This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA
  ☆13Updated 10 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆23Updated 3 years ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆121Updated 10 years ago
• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆15Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆56Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated 2 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆67Updated 3 years ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆124Updated 8 months ago
• baselkelziye / PCIe_Scrambler
  PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…
  ☆14Updated 4 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆160Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆35Updated 2 years ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆30Updated 2 months ago
• jonlwowski012 / OV7670_NEXYS4_Verilog
  This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
  ☆31Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆120Updated last month
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆160Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆137Updated 5 years ago
• makararasi / UVM_AXI4-Stream
  ☆14Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆157Updated 6 years ago