4a1c0 / RV32i-VerilogLinks
Simple RiscV core for academic purpose.
☆22Updated 5 years ago
Alternatives and similar repositories for RV32i-Verilog
Users that are interested in RV32i-Verilog are comparing it to the libraries listed below
Sorting:
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Basic RISC-V Test SoC☆139Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- RISC-V Verification Interface☆100Updated 2 months ago
- Mathematical Functions in Verilog☆93Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆58Updated 5 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Verilog digital signal processing components☆146Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆47Updated 3 weeks ago
- SpinalHDL Hardware Math Library☆89Updated last year
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- RISC-V Nox core☆66Updated 2 weeks ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- I2C controller core☆47Updated 2 years ago
- ☆41Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago