Simple RiscV core for academic purpose.
☆22Apr 29, 2020Updated 6 years ago
Alternatives and similar repositories for RV32i-Verilog
Users that are interested in RV32i-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 10 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- USB2.0 Device Controller IP Core☆21Aug 18, 2023Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- ⌨️ RISC-V NS16550A UART driver☆11Mar 24, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 4 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 4 years ago
- 中科大大物实验数据☆14Mar 5, 2022Updated 4 years ago
- zero-riscy CPU Core☆19Jun 10, 2018Updated 8 years ago
- 中科大 2017 级数字电路实验/组成原理实验的同学经验和资料分享☆12Oct 25, 2019Updated 6 years ago
- Computer Architecture UIUC SP 2018☆15May 4, 2018Updated 8 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- Repository to store all design and testbench files for Senior Design☆23Apr 16, 2020Updated 6 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A vision transformer based framework for classifying executable images as benign or malicious☆11Mar 19, 2024Updated 2 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- Repository for USTC 2021 Spring Database Labs☆10Jul 6, 2021Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- ☆13Apr 24, 2022Updated 4 years ago
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- Arduino sketches for the TinkerRTK base station and rover communicating over a WiFi network☆11Oct 7, 2023Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆20Aug 3, 2021Updated 5 years ago
- ☆15Sep 27, 2022Updated 4 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 9 years ago
- RV32I single cycle simulation on open-source software Logisim.☆23Oct 8, 2022Updated 3 years ago
- Small applet for rotating the screen on Unity Desktop☆16Jul 13, 2020Updated 6 years ago
- Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.☆14Dec 5, 2019Updated 6 years ago
- Benchmarking execution time of AlexNet CNN on FPGA and GPU. Developed AlexNet in opencl.☆11Oct 9, 2019Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆15May 17, 2025Updated last year
- SPI Slave for FPGA in Verilog and VHDL☆233May 11, 2024Updated 2 years ago
- ☆12Jan 21, 2021Updated 5 years ago
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12May 14, 2017Updated 9 years ago
- ☆27May 31, 2021Updated 5 years ago
- Watch video on youtube☆19Nov 7, 2025Updated 10 months ago
- USTC computer practice code and interesting small projects☆13Apr 24, 2020Updated 6 years ago