Simple RiscV core for academic purpose.
☆22Apr 29, 2020Updated 6 years ago
Alternatives and similar repositories for RV32i-Verilog
Users that are interested in RV32i-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- computer hardware system including ps2/vga with tank war game in verilog and mips☆21Oct 21, 2015Updated 11 years ago
- Behavioural design of UART with a FIFO buffer in verilog☆13Aug 25, 2021Updated 5 years ago
- TEMPORARY FORK of the riscv-compliance repository☆34Mar 31, 2021Updated 5 years ago
- RV32I single cycle simulation on open-source software Logisim.☆23Oct 8, 2022Updated 4 years ago
- A sparse matrix-vector parallel multiplication implementation using MPI☆10Mar 15, 2015Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- ⌨️ RISC-V NS16550A UART driver☆11Mar 24, 2021Updated 5 years ago
- RISCV SoftCPU Contest 2018☆14Nov 17, 2018Updated 7 years ago
- ☆18Jul 30, 2021Updated 5 years ago
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- ☆12Updated this week
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- zero-riscy CPU Core☆19Jun 10, 2018Updated 8 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Oct 13, 2026Updated 3 weeks ago
- S2-LP driver library, low-level and easy-to-port☆10Dec 29, 2021Updated 4 years ago
- Repository for USTC 2021 Spring Database Labs☆10Jul 6, 2021Updated 5 years ago
- USB2.0 Device Controller IP Core☆21Aug 18, 2023Updated 3 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 9 years ago
- 本Project結合了碩士班上課的內容、書籍「CPU自制入門」、書籍「自己動手寫CPU」來完成一個MIPS32架構的CPU。☆24Feb 23, 2022Updated 4 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- RISC-V microcontroller IP for embedded, FPGA and ASIC applications☆204Nov 1, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆11Jul 26, 2017Updated 9 years ago
- Benchmarking execution time of AlexNet CNN on FPGA and GPU. Developed AlexNet in opencl.☆11Oct 9, 2019Updated 7 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Repository to store all design and testbench files for Senior Design☆23Apr 16, 2020Updated 6 years ago
- ☆15May 17, 2025Updated last year
- A simple RISC-V CPU written in Verilog.☆73Mar 16, 2026Updated 7 months ago
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12May 14, 2017Updated 9 years ago
- ☆15Sep 27, 2022Updated 4 years ago
- ☆12Jan 21, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated last year
- SPI Slave for FPGA in Verilog and VHDL☆234May 11, 2024Updated 2 years ago
- The repo contains code example and demo for using the make build system☆19Jul 22, 2023Updated 3 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- STM32 RFID Reader / Writer☆16May 24, 2014Updated 12 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆16Oct 5, 2025Updated last year
Are these results useful?