Alternatives and similar repositories for neorv32-riscof

Users that are interested in neorv32-riscof are comparing it to the libraries listed below

• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆93Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆120Updated 8 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆89Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆32Updated last year
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆97Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆98Updated 3 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• pulp-platform / pulp-ethernet
  ☆14Updated 2 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆56Updated this week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 6 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆42Updated this week
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆47Updated 7 months ago