stnolting / neorv32-riscofLinks
✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
☆34Updated this week
Alternatives and similar repositories for neorv32-riscof
Users that are interested in neorv32-riscof are comparing it to the libraries listed below
Sorting:
- The multi-core cluster of a PULP system.☆108Updated last week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- Naive Educational RISC V processor☆88Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 7 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago
- 64-bit multicore Linux-capable RISC-V processor☆97Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated 3 weeks ago
- A pipelined RISC-V processor☆61Updated last year
- Demo SoC for SiliconCompiler.☆61Updated last week
- PicoRV☆44Updated 5 years ago
- Raptor end-to-end FPGA Compiler and GUI☆85Updated 9 months ago
- Simple runtime for Pulp platforms☆49Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆96Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last month
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆38Updated last month
- Generic Register Interface (contains various adapters)☆130Updated 2 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- SoftCPU/SoC engine-V☆55Updated 6 months ago
- RISC-V Nox core☆68Updated 2 months ago
- ☆33Updated 2 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- FPGA Assembly (FASM) Parser and Generator☆96Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- CV32E40X Design-Verification environment☆13Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 months ago