32 bit RISC-V CPU implementation in Verilog
☆34Feb 9, 2022Updated 4 years ago
Alternatives and similar repositories for emil-risc-v
Users that are interested in emil-risc-v are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of RISC-V RV32I☆33Aug 30, 2022Updated 3 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆71May 8, 2021Updated 5 years ago
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆43Dec 5, 2019Updated 6 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆380Jan 12, 2018Updated 8 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated 2 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆133Dec 17, 2023Updated 2 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Aug 3, 2021Updated 5 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆178Nov 2, 2020Updated 5 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 9 months ago
- 6502 SoC for the Tang Nano 20k FPGA Board☆24Updated this week
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- Verilog Project☆22Aug 30, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- VGA interface using Raspberry Pi as a PCXT graphics card emulator☆13Jun 30, 2020Updated 6 years ago
- ☆15Jul 5, 2019Updated 7 years ago
- Sparc emulator☆11May 19, 2018Updated 8 years ago
- ☆35Nov 24, 2021Updated 4 years ago
- RISC-V Ibex core with Wishbone B4 interface☆22May 30, 2026Updated 2 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆37Aug 12, 2020Updated 6 years ago
- Motorola 68000 (32 bit with unneeded instructions removed) in an FPGA.☆17Mar 24, 2024Updated 2 years ago
- Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.☆157Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Dec 1, 2024Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 3 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆242May 20, 2025Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 9 months ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆228Nov 13, 2024Updated last year