emilbiju / emil-risc-v
32 bit RISC-V CPU implementation in Verilog
☆22Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for emil-risc-v
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆67Updated 10 months ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆20Updated 3 years ago
- 32-bit soft RISCV processor for FPGA applications☆14Updated 11 months ago
- A simple DDR3 memory controller☆51Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆52Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- Simple 8-bit UART realization on Verilog HDL.☆78Updated 6 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- Simple RiscV core for academic purpose.☆21Updated 4 years ago
- Pipelined RISC-V RV32I Core in Verilog☆35Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated this week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆61Updated last year
- Basic RISC-V Test SoC☆104Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- This repository contains the design files of RISC-V Pipeline Core☆30Updated last year
- Simple sram controller in verilog.☆30Updated 8 years ago
- Another tiny RISC-V implementation☆52Updated 3 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆27Updated 10 months ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- Mathematical Functions in Verilog☆84Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆78Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 2 weeks ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- RISC-V Verification Interface☆74Updated 2 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆114Updated 4 years ago