32 bit RISC-V CPU implementation in Verilog
☆34Feb 9, 2022Updated 4 years ago
Alternatives and similar repositories for emil-risc-v
Users that are interested in emil-risc-v are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆14Feb 24, 2026Updated 3 months ago
- Single-cycle MIPS processor in Verilog HDL.☆10May 1, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A verilog based 5-stage pipelined RISC-V Processor code.☆40Mar 25, 2020Updated 6 years ago
- Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).☆18Aug 28, 2025Updated 9 months ago
- Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU☆14Jan 17, 2022Updated 4 years ago
- Verilog Project☆20Aug 30, 2021Updated 4 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆66Jul 5, 2024Updated last year
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- ☆19Feb 26, 2024Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆170Nov 2, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆14Aug 3, 2021Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆149Oct 2, 2025Updated 8 months ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- A simple, working, 32-bit ALU design.☆14Dec 26, 2014Updated 11 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 7 months ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆42Dec 5, 2019Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A 10bit SAR ADC in Sky130☆36Dec 4, 2022Updated 3 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- VGA interface using Raspberry Pi as a PCXT graphics card emulator☆13Jun 30, 2020Updated 5 years ago
- Sparc emulator☆11May 19, 2018Updated 8 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- ☆35Nov 24, 2021Updated 4 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- Motorola 68000 (32 bit with unneeded instructions removed) in an FPGA.☆17Mar 24, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆18Oct 6, 2024Updated last year
- Single Cycle CPU using the RV32I Base Instruction set☆22Nov 5, 2025Updated 7 months ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆30Feb 19, 2025Updated last year
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆37Aug 12, 2020Updated 5 years ago
- PYNQ for Zybo board☆15Jan 30, 2026Updated 4 months ago