emilbiju / emil-risc-v
32 bit RISC-V CPU implementation in Verilog
☆27Updated 3 years ago
Alternatives and similar repositories for emil-risc-v:
Users that are interested in emil-risc-v are comparing it to the libraries listed below
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆80Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆26Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- Simple 8-bit UART realization on Verilog HDL.☆97Updated 9 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆88Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆33Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆123Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆51Updated this week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Updated 2 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆38Updated 7 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- This repository contains the design files of RISC-V Pipeline Core☆35Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆43Updated 3 years ago
- Repository for system verilog labs from cadence☆10Updated 5 years ago
- Basic RISC-V Test SoC☆112Updated 5 years ago
- UVM and System Verilog Manuals☆39Updated 6 years ago
- Simple RiscV core for academic purpose.☆22Updated 4 years ago
- An implementation of the CORDIC algorithm in Verilog.☆87Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆80Updated 5 years ago
- DDR2 memory controller written in Verilog☆73Updated 12 years ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆64Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆40Updated 11 months ago