emilbiju / emil-risc-vLinks
32 bit RISC-V CPU implementation in Verilog
☆31Updated 3 years ago
Alternatives and similar repositories for emil-risc-v
Users that are interested in emil-risc-v are comparing it to the libraries listed below
Sorting:
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Verilog implementation of multi-stage 32-bit RISC-V processor☆116Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- Basic RISC-V Test SoC☆139Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆52Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆45Updated 4 years ago
- Simple RiscV core for academic purpose.☆22Updated 5 years ago
- Verilog UART☆178Updated 12 years ago
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- Arduino compatible Risc-V Based SOC☆155Updated last year
- Single Cycle CPU using the RV32I Base Instruction set☆16Updated 2 years ago
- RISC-V microcontroller IP core developed in Verilog☆176Updated 3 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆185Updated 3 weeks ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆92Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago
- 64-bit multicore Linux-capable RISC-V processor☆95Updated 3 months ago
- RISC-V System on Chip Template☆159Updated last week
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆89Updated 2 years ago
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago