phoeniX-Digital-Design / phoeniXLinks
A Reconfigurable RISC-V Core for Approximate Computing
☆128Updated 6 months ago
Alternatives and similar repositories for phoeniX
Users that are interested in phoeniX are comparing it to the libraries listed below
Sorting:
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 11 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 2 months ago
- RISC-V Nox core☆71Updated 5 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆77Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆53Updated 3 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆178Updated this week
- ☆43Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 3 weeks ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆95Updated 6 months ago
- BlackParrot on Zynq☆47Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- ☆33Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- ☆45Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- APB master and slave developed in RTL.☆20Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- Complete tutorial code.☆22Updated last year
- Verilog RTL Design☆46Updated 4 years ago