phoeniX-Digital-Design / phoeniXLinks
A Reconfigurable RISC-V Core for Approximate Computing
☆128Updated 6 months ago
Alternatives and similar repositories for phoeniX
Users that are interested in phoeniX are comparing it to the libraries listed below
Sorting:
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 11 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 2 months ago
- RISC-V Nox core☆71Updated 5 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆77Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆178Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆96Updated 9 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- Basic RISC-V Test SoC☆162Updated 6 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆95Updated 6 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 3 weeks ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆111Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- ☆33Updated last month
- SystemVerilog Tutorial☆185Updated 3 weeks ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- ☆43Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆146Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- RISC-V Verification Interface☆134Updated 2 weeks ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 2 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago