KULeuven-MICAS / streamLinks
Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
☆64Updated 6 months ago
Alternatives and similar repositories for stream
Users that are interested in stream are comparing it to the libraries listed below
Sorting:
- FSA: Fusing FlashAttention within a Single Systolic Array☆84Updated 5 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆70Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆46Updated 3 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆61Updated 9 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- ☆54Updated last month
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- ☆39Updated 3 weeks ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆53Updated 5 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆68Updated 2 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆107Updated 8 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆85Updated 8 months ago
- ☆72Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- ☆32Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- ☆48Updated 4 years ago
- ☆80Updated last week
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- ☆42Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year