mit-emze / cimloopLinks
☆65Updated 2 weeks ago
Alternatives and similar repositories for cimloop
Users that are interested in cimloop are comparing it to the libraries listed below
Sorting:
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆62Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- ☆35Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆59Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆157Updated last week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 3 months ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆51Updated 4 months ago
- ☆48Updated 4 years ago
- ☆41Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆43Updated 5 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆31Updated last month
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆102Updated 4 months ago
- ☆41Updated 2 weeks ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A co-design architecture on sparse attention☆51Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆101Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 4 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆137Updated 2 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆146Updated 6 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆23Updated last month
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆87Updated 4 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- ☆49Updated last month