Alternatives and similar repositories for messy_notes

Users that are interested in messy_notes are comparing it to the libraries listed below

• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 11 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆26Updated last year
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆13Updated 6 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆36Updated last month
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆17Updated 7 years ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆38Updated 4 years ago
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆29Updated 5 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆27Updated 2 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆37Updated 7 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆35Updated last year
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆15Updated 3 years ago
• pulp-platform / ITA
  ☆60Updated 7 months ago
• kuladeepsaireddy / OpenNoc
  ☆39Updated 6 years ago
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• synxlin / branch-predictor-simulator
  A C version of Branch Predictor Simulator
  ☆18Updated last year
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆131Updated 9 months ago
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆32Updated last month
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆10Updated 4 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆49Updated last week
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• OSCPU / yosys-sta
  ☆87Updated last month