chsgcxy / messy_notes
all kind of notes, I maybe sort this in the future
☆10Updated 2 weeks ago
Alternatives and similar repositories for messy_notes:
Users that are interested in messy_notes are comparing it to the libraries listed below
- YSYX RISC-V Project NJU Study Group☆13Updated last month
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- ☆41Updated 6 years ago
- ☆25Updated 4 years ago
- 关于移植模型至gemmini的文档☆21Updated 2 years ago
- 中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程☆24Updated 4 years ago
- note about IC knowledge☆9Updated 2 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆22Updated 3 months ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- ☆29Updated 5 years ago
- ☆12Updated 8 months ago
- RTL generator for SpGEMM☆9Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆24Updated 5 years ago
- 自建 chisel 工程模板☆12Updated last year
- An almost empty chisel project as a starting point for hardware design☆30Updated 3 weeks ago
- ☆17Updated last year
- ☆79Updated last week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆23Updated this week
- EE577b-Course-Project☆16Updated 4 years ago
- ☆9Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 8 months ago
- ☆21Updated last year