AWB-Tools / awb
Architect's workbench
☆9Updated 8 years ago
Related projects: ⓘ
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- ☆15Updated this week
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- ☆24Updated 8 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- FGPU is a soft GPU architecture general purpose computing☆53Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆41Updated 3 years ago
- SoCRocket - Core Repository☆32Updated 7 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last year
- ☆14Updated 3 years ago
- ☆84Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆35Updated 5 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆25Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- The RTL source for AnyCore RISC-V☆29Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆17Updated this week
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 6 years ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆13Updated 9 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- ☆12Updated 9 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- Documentation for the entire CGRAFlow☆17Updated 3 years ago