pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs)
☆20Jan 12, 2023Updated 3 years ago
Alternatives and similar repositories for pLUTo
Users that are interested in pLUTo are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆16Sep 24, 2020Updated 6 years ago
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆18May 17, 2024Updated 2 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated 2 years ago
- ☆12Jan 22, 2026Updated 9 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆18Aug 2, 2019Updated 7 years ago
- Source code & scripts for experimental characterization and demonstration of performing NOT and up to 16-input AND, NAND, OR, and NOR ope…☆15Apr 9, 2024Updated 2 years ago
- NATSA is the first near-data-processing accelerator for time series analysis based on the Matrix Profile (SCRIMP) algorithm. NATSA exploi…☆17Jun 14, 2023Updated 3 years ago
- Python wrapper for the timeloop project.☆11Oct 3, 2025Updated last year
- Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…☆36Sep 12, 2025Updated last year
- SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) ar…☆79Jun 29, 2022Updated 4 years ago
- ApHMM-GPU is the first GPU implementation of the Baum-Welch algorithm for profile Hidden Markov Models (pHMMs). It includes many of the s…☆11Jul 21, 2022Updated 4 years ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 8 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆19Nov 15, 2022Updated 3 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆17Sep 15, 2022Updated 4 years ago
- Source code for the software implementation of SeGraM proposed in our ISCA 2022 paper: Senol Cali et. al., "SeGraM: A Universal Hardware …☆13Nov 3, 2022Updated 3 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆12Jan 23, 2026Updated 9 months ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆40Oct 23, 2023Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆77Sep 15, 2026Updated last month
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆82Dec 19, 2022Updated 3 years ago
- ☆35Apr 20, 2021Updated 5 years ago
- SW Library for Samsung PNM (including functional simulator)☆11Nov 2, 2023Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆83Dec 11, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆12Feb 12, 2016Updated 10 years ago
- ☆12Sep 19, 2026Updated last month
- ☆13Mar 14, 2023Updated 3 years ago
- Mapper for digital PIM architectures☆33Sep 1, 2025Updated last year
- ☆16Apr 10, 2023Updated 3 years ago
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆41Mar 1, 2019Updated 7 years ago
- 3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit (MICRO 2022)☆29May 19, 2023Updated 3 years ago
- AIM, A Framework for High-throughput Sequence Alignment using Real Processing-in-Memory Systems, Bioinformatics, btad155, https://doi.or…☆24Apr 12, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Mar 30, 2022Updated 4 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Apr 5, 2022Updated 4 years ago
- Metasys is the first open-source FPGA-based infrastructure with a prototype in a RISC-V core, to enable the rapid implementation and eval…☆16Jan 20, 2023Updated 3 years ago
- Processing in Memory Emulation☆32Feb 24, 2023Updated 3 years ago
- Open DRAM Model v1.0 (Access Transistors & High-Voltage Periphery Transistors for 6F²/4F²/3D DRAM)☆33Jun 16, 2026Updated 4 months ago
- Detailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new ta…☆12May 3, 2024Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago