CMU-SAFARI / pLUToLinks
pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs)
☆16Updated 2 years ago
Alternatives and similar repositories for pLUTo
Users that are interested in pLUTo are comparing it to the libraries listed below
Sorting:
- ☆25Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆20Updated last year
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆29Updated last year
- ☆22Updated 8 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- NeuraChip Accelerator Simulator☆14Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆15Updated last year
- Heterogenous ML accelerator☆19Updated 5 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 3 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- ☆36Updated 4 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- ☆65Updated 4 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11Updated 3 years ago
- ☆13Updated 5 years ago
- Fibertree emulator☆14Updated 11 months ago
- ☆14Updated 4 years ago
- SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) ar…☆77Updated 3 years ago