GoWest279 / XuanTie-C910-FPGALinks
☆20Updated 3 years ago
Alternatives and similar repositories for XuanTie-C910-FPGA
Users that are interested in XuanTie-C910-FPGA are comparing it to the libraries listed below
Sorting:
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- UVM实战随书源码☆52Updated 6 years ago
- ☆67Updated 9 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- soc integration script and integration smoke script☆23Updated 2 years ago
- This is the repository for the IEEE version of the book☆67Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- AXI DMA 32 / 64 bits☆115Updated 11 years ago
- ☆36Updated 9 years ago
- AHB3-Lite Interconnect☆90Updated last year
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- round robin arbiter☆74Updated 11 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆43Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- ☆58Updated 2 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆45Updated 3 years ago
- SDRAM controller with AXI4 interface☆95Updated 5 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- ☆23Updated 4 months ago
- An AXI4 crossbar implementation in SystemVerilog☆161Updated last month
- RTL Verilog library for various DSP modules☆90Updated 3 years ago