GoWest279 / XuanTie-C910-FPGALinks
☆22Updated 3 years ago
Alternatives and similar repositories for XuanTie-C910-FPGA
Users that are interested in XuanTie-C910-FPGA are comparing it to the libraries listed below
Sorting:
- ☆73Updated 9 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆115Updated 4 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- ☆38Updated 10 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- This is the repository for the IEEE version of the book☆77Updated 5 years ago
- UVM实战随书源码☆57Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 13 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆195Updated 3 months ago
- AXI总线连接器☆105Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- ☆66Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆108Updated 2 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆71Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆49Updated 3 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆26Updated 5 years ago
- ☆47Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆93Updated last year
- AHB3-Lite Interconnect☆107Updated last year