GoWest279 / XuanTie-C910-FPGALinks
☆22Updated 3 years ago
Alternatives and similar repositories for XuanTie-C910-FPGA
Users that are interested in XuanTie-C910-FPGA are comparing it to the libraries listed below
Sorting:
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆83Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆108Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆108Updated 2 years ago
- This is the repository for the IEEE version of the book☆75Updated 5 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- ☆71Updated 9 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- ☆16Updated 3 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- round robin arbiter☆77Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆180Updated 2 months ago
- ☆45Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- ☆65Updated 3 years ago
- OpenXuantie - OpenE902 Core☆161Updated last year
- soc integration script and integration smoke script☆24Updated 3 years ago
- UVM实战随书源码☆56Updated 6 years ago
- AHB3-Lite Interconnect☆96Updated last year
- ☆74Updated 4 years ago
- RTL Verilog library for various DSP modules☆92Updated 3 years ago
- ☆38Updated 10 years ago