alireza-shirzad / Cordic_tanhLinks
Verilog and matlab implementation of tanh using Cordic algorithm
☆11Updated 5 years ago
Alternatives and similar repositories for Cordic_tanh
Users that are interested in Cordic_tanh are comparing it to the libraries listed below
Sorting:
- YSYX RISC-V Project NJU Study Group☆15Updated 9 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- ☆36Updated 6 years ago
- ☆26Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆11Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- ☆12Updated 9 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- ☆20Updated 3 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆64Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- AXI Interconnect☆53Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- ☆14Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆37Updated 10 years ago
- ☆10Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆40Updated 3 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- ☆13Updated 8 years ago