emmanouil-komninos / jtag_vip_uvmLinks
☆12Updated 9 years ago
Alternatives and similar repositories for jtag_vip_uvm
Users that are interested in jtag_vip_uvm are comparing it to the libraries listed below
Sorting:
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- ☆26Updated 4 years ago
- Verification IP for SPI protocol☆18Updated 5 years ago
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Verification IP for UART protocol☆19Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- ☆20Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- ☆20Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- ☆17Updated 10 years ago
- ☆14Updated 6 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- ☆15Updated 2 years ago
- soc integration script and integration smoke script☆23Updated 2 years ago
- UVM Clock and Reset Agent☆13Updated 8 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago