Alternatives and similar repositories for OOP-2015:

Users that are interested in OOP-2015 are comparing it to the libraries listed below

• nhandyal / Verilog-Spectrum-Analyzer
  FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
  ☆14Updated 12 years ago
• Deverne-labs / TinyML-Zybo
  This repository is a collection of designs invloving FPGAs and AI technologies.
  ☆14Updated 2 years ago
• Daniel-And-Jorge / 6.111-Final-Project
  ☆11Updated 7 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆19Updated last year
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated this week
• Jaffe- / ccsds123
  VHDL implementation of CCSDS123 compression standard
  ☆5Updated 5 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆51Updated last year
• kunalg123 / sky130RTLDesignAndSynthesisWorkshop
  ☆11Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆17Updated 4 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• mattvenn / simulate-gate
  Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
  ☆13Updated 10 months ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 2 years ago
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆31Updated 5 years ago
• JohnDMcMaster / xilinx-usb-driver
  Mirror of git://git.zerfleddert.de/usb-driver
  ☆19Updated 11 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• sehugg / fpga-examples
  FPGA examples for 8bitworkshop.com
  ☆29Updated 5 years ago
• RobRoyce / fpga_mouse_controller_basys3
  USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and valid…
  ☆13Updated 3 years ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆15Updated 4 years ago
• olofk / qerv
  ☆14Updated 3 months ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• fransschreuder / 8b10b_VHDL
  An 8b10b decoder and encoder in logic in VHDL
  ☆18Updated 3 years ago
• ZipCPU / wbpmic
  Wishbone controller for a MEMs microphone
  ☆14Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• fm4dd / gatemate-riscv
  RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
  ☆12Updated 2 weeks ago
• zeroasiccorp / ebrick-demo
  Demo: how to create a custom EBRICK
  ☆17Updated 3 months ago
• chili-chips-ba / openeye-CamSI
  A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …
  ☆40Updated last week