OOP-2015-Sem1 / OOP-2015
Main repo of the OOP class
☆11Updated 7 years ago
Alternatives and similar repositories for OOP-2015:
Users that are interested in OOP-2015 are comparing it to the libraries listed below
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆14Updated 12 years ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆12Updated 3 years ago
- Openhardware educational platform based on the ideas of the ulx3s and Gecko4Education☆10Updated 4 months ago
- ☆16Updated 7 years ago
- FPGA examples for 8bitworkshop.com☆29Updated 5 years ago
- Verilog source code for book: Computer Architecture Tutorial☆25Updated 3 years ago
- ☆11Updated 7 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 2 months ago
- Custom 64-bit pipelined RISC processor☆17Updated 7 months ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆14Updated last year
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated this week
- Amber ARM-compatible core☆13Updated 10 years ago
- Design a CPU in VHDL☆10Updated 2 years ago
- A SoC for DOOM☆16Updated 3 years ago
- Verilog VPI VGA Simulator using SDL☆12Updated 10 years ago
- This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.☆11Updated 3 years ago
- ☆11Updated 2 years ago
- 32-bit RISC-V based processor with memory controler☆15Updated 2 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Updated 10 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆16Updated last year
- ☆10Updated 5 years ago
- A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems an…☆13Updated 4 years ago
- RV32I single cycle simulation on open-source software Logisim.☆19Updated 2 years ago
- Project 2.2 Frequency counter☆11Updated 2 months ago
- Verilog SDR SDRAM controller for FPGA Xilinx and Lattice☆16Updated 4 years ago
- VGA-compatible text mode functionality☆16Updated 4 years ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- Data Structures and Algorithms lab repository☆11Updated 9 years ago