kaitoukito / Integrated-Circuit-TextbooksLinks
Collect some IC textbooks for learning.
☆150Updated 2 years ago
Alternatives and similar repositories for Integrated-Circuit-Textbooks
Users that are interested in Integrated-Circuit-Textbooks are comparing it to the libraries listed below
Sorting:
- ☆176Updated last month
- AXI协议规范中文翻译版☆159Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- CPU Design Based on RISCV ISA☆118Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆105Updated 5 months ago
- ☆43Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆205Updated 2 months ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆41Updated 4 years ago
- AXI总线连接器☆103Updated 5 years ago
- some knowleage about SystemC/TLM etc.☆25Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆117Updated 12 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆128Updated 2 months ago
- Some useful documents of Synopsys☆77Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆148Updated 3 weeks ago
- ☆86Updated 3 months ago
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- IC implementation of Systolic Array for TPU☆263Updated 9 months ago
- A Chisel RTL generator for network-on-chip interconnects☆207Updated 2 months ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆52Updated 11 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- ☆43Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆211Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆93Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago