kaitoukito / Integrated-Circuit-TextbooksLinks
Collect some IC textbooks for learning.
☆138Updated 2 years ago
Alternatives and similar repositories for Integrated-Circuit-Textbooks
Users that are interested in Integrated-Circuit-Textbooks are comparing it to the libraries listed below
Sorting:
- ☆158Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆154Updated 3 weeks ago
- AXI协议规范中文翻译版☆150Updated 2 years ago
- CPU Design Based on RISCV ISA☆110Updated 11 months ago
- Some useful documents of Synopsys☆72Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- ☆42Updated 3 years ago
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- IC implementation of Systolic Array for TPU☆246Updated 7 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆159Updated 5 years ago
- AXI总线连接器☆97Updated 5 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆205Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆101Updated 3 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆59Updated 3 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆86Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- ☆86Updated last month
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆37Updated 4 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆198Updated 2 months ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆115Updated 12 years ago
- Awesome ASIC design verification☆300Updated 3 years ago
- ☆145Updated this week
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 9 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆28Updated 2 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago
- some knowleage about SystemC/TLM etc.☆24Updated last year