Alternatives and similar repositories for Integrated-Circuit-Textbooks:

Users that are interested in Integrated-Circuit-Textbooks are comparing it to the libraries listed below

• RV-BOSC / OpenNoC
  ☆131Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆138Updated last month
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆141Updated 2 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆67Updated 3 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆97Updated 9 months ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆69Updated last week
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆94Updated 4 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆142Updated last month
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆96Updated 5 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆26Updated 2 years ago
• OSCPU / ysyxSoC
  ☆80Updated last month
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆194Updated last year
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆207Updated 5 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆24Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆191Updated 2 weeks ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆82Updated 3 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆179Updated 7 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆88Updated last month
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆414Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆184Updated last year
• ForrestBlue / cortexm0ds
  ☆59Updated 9 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆49Updated 6 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆35Updated 4 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆166Updated 6 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆41Updated 7 months ago