This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
☆57Aug 12, 2017Updated 8 years ago
Alternatives and similar repositories for Verilog_Calculator_Matrix_Multiplication
Users that are interested in Verilog_Calculator_Matrix_Multiplication are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design for 4 x 4 Matrix Multiplication using Verilog☆33Jun 9, 2015Updated 11 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- Computer organization lab source for 2025☆10Jun 10, 2025Updated last year
- ☆13Jul 2, 2016Updated 10 years ago
- Project Trellis database☆14Sep 15, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆36May 12, 2020Updated 6 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Cryptonight Monero Verilog code for ASIC☆20Mar 29, 2018Updated 8 years ago
- Implementing Different Adder Structures in Verilog☆76Sep 3, 2019Updated 6 years ago
- HDL implementation of a pipelined multilayer perceptron (neural network)☆17Sep 14, 2015Updated 10 years ago
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- 3×3脉动阵列乘法器☆50Sep 18, 2019Updated 6 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆45Mar 22, 2019Updated 7 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆31Feb 21, 2024Updated 2 years ago
- AXI4-Stream FIR filter IP☆19Nov 4, 2022Updated 3 years ago
- ☆10Aug 30, 2024Updated last year
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- ☆35Apr 20, 2021Updated 5 years ago
- course design☆23Feb 28, 2018Updated 8 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- 数字图像处理彩色图像复原☆16Jun 21, 2021Updated 5 years ago
- RTL implementation of Flex-DPE.☆117Feb 22, 2020Updated 6 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 🤖 An automated NTU Thesis LaTeX continuous integration and continuous deploying service built up with GitHub Actions.☆10May 8, 2020Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Hardware Description Language Translator☆17Jun 9, 2026Updated 3 weeks ago
- Source code for 'Beginning Arduino' by Michael McRoberts☆10Mar 28, 2017Updated 9 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆50Oct 21, 2016Updated 9 years ago