pontazaricardo / Verilog_Calculator_Matrix_MultiplicationLinks
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
☆53Updated 8 years ago
Alternatives and similar repositories for Verilog_Calculator_Matrix_Multiplication
Users that are interested in Verilog_Calculator_Matrix_Multiplication are comparing it to the libraries listed below
Sorting:
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- ☆39Updated 6 years ago
- IC implementation of TPU☆142Updated 6 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- ☆71Updated 7 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆173Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆196Updated 3 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆236Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- ☆66Updated 3 years ago
- AXI总线连接器☆105Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago