pontazaricardo / Verilog_Calculator_Matrix_MultiplicationLinks
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
☆53Updated 8 years ago
Alternatives and similar repositories for Verilog_Calculator_Matrix_Multiplication
Users that are interested in Verilog_Calculator_Matrix_Multiplication are comparing it to the libraries listed below
Sorting:
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- ☆38Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆39Updated 3 years ago
- IC implementation of TPU☆140Updated 5 years ago
- ☆65Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- ☆71Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆171Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆235Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- An AXI4 crossbar implementation in SystemVerilog☆193Updated 3 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆138Updated 7 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- 3×3脉动阵列乘法器☆49Updated 6 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 6 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- round robin arbiter☆77Updated 11 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆70Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year