Design for 4 x 4 Matrix Multiplication using Verilog
☆35Jun 9, 2015Updated 10 years ago
Alternatives and similar repositories for Matrix-Multiplication
Users that are interested in Matrix-Multiplication are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆56Aug 12, 2017Updated 8 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆100Apr 30, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…☆23May 15, 2024Updated last year
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆30Feb 21, 2024Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Jul 17, 2023Updated 2 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- ☆96Apr 21, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 3×3脉动阵列乘法器☆51Sep 18, 2019Updated 6 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆27Jun 18, 2020Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated last month
- ☆30Oct 4, 2017Updated 8 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆35Apr 20, 2021Updated 5 years ago
- Tiny matrix multiplication ASIC with 4-bit math☆12Apr 19, 2024Updated 2 years ago
- This source code (in Python) is a preliminary implementation of my quadratic-time positive integer matrix multiplication.☆10Nov 23, 2022Updated 3 years ago
- An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics…☆10Jul 27, 2020Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆64Nov 7, 2019Updated 6 years ago
- Real-time Audio Processing through FIR filters on Basys-3 FPGA and Pmod I2S2☆16Feb 1, 2023Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Matrix multiplication on multiple Nios II cores☆16Feb 12, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 大一上学期C++课程设计——学生成绩管理系统（QT项目）☆13Jun 22, 2022Updated 3 years ago
- 16QAM modulation and demodulation by Verilog☆22Jan 4, 2021Updated 5 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago
- Fixed Point Kalman filter for fpga☆25May 10, 2020Updated 5 years ago
- 基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）☆52Apr 23, 2020Updated 6 years ago
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago