Design for 4 x 4 Matrix Multiplication using Verilog
☆35Jun 9, 2015Updated 10 years ago
Alternatives and similar repositories for Matrix-Multiplication
Users that are interested in Matrix-Multiplication are comparing it to the libraries listed below
Sorting:
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Apr 30, 2019Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 4 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆17May 26, 2021Updated 4 years ago
- Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…☆23May 15, 2024Updated last year
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- The code for Joint Neural Architecture Search and Quantization☆14Apr 10, 2019Updated 6 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆29Feb 21, 2024Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- A curated list for Efficient Large Language Models☆11Mar 25, 2024Updated last year
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- ☆90Updated this week
- 3×3脉动阵列乘法器☆51Sep 18, 2019Updated 6 years ago
- This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human er…☆18Mar 12, 2026Updated last week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆27Jun 18, 2020Updated 5 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- ☆29Oct 4, 2017Updated 8 years ago
- ☆16Jan 20, 2021Updated 5 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- ☆36Apr 20, 2021Updated 4 years ago
- Tiny matrix multiplication ASIC with 4-bit math☆11Apr 19, 2024Updated last year
- This source code (in Python) is a preliminary implementation of my quadratic-time positive integer matrix multiplication.☆10Nov 23, 2022Updated 3 years ago
- An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics…☆10Jul 27, 2020Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Nov 7, 2019Updated 6 years ago
- Real-time Audio Processing through FIR filters on Basys-3 FPGA and Pmod I2S2☆14Feb 1, 2023Updated 3 years ago
- Fixed Point Kalman filter for fpga☆24May 10, 2020Updated 5 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Sep 16, 2023Updated 2 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Matrix multiplication on multiple Nios II cores☆16Feb 12, 2020Updated 6 years ago
- 16QAM modulation and demodulation by Verilog☆22Jan 4, 2021Updated 5 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- This is a custom library for data processing, visualization and machine learning tools.☆14Dec 28, 2025Updated 2 months ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆52Apr 23, 2020Updated 5 years ago