vrishbhan / Matrix-Multiplication
Design for 4 x 4 Matrix Multiplication using Verilog
☆31Updated 9 years ago
Alternatives and similar repositories for Matrix-Multiplication:
Users that are interested in Matrix-Multiplication are comparing it to the libraries listed below
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Verilog implementation of Softmax function☆59Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- tpu-systolic-array-weight-stationary☆22Updated 3 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆47Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- ☆31Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆28Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- AIChip 2021 project, NCKU☆16Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆146Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆27Updated 4 years ago
- ☆63Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆54Updated last month
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆19Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago