zhouzaixin / arm_socView external linksLinks
☆14Jun 30, 2019Updated 6 years ago
Alternatives and similar repositories for arm_soc
Users that are interested in arm_soc are comparing it to the libraries listed below
Sorting:
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- ☆10May 26, 2023Updated 2 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- UVM examples☆14May 1, 2015Updated 10 years ago
- ☆13Jun 4, 2020Updated 5 years ago
- Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.☆12Sep 29, 2022Updated 3 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 5 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 5 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 7 years ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- Implementation of the PCIe physical layer☆60Jul 11, 2025Updated 7 months ago
- a very simple risc_cpu verification demo with uvm☆26Apr 28, 2019Updated 6 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆25Mar 21, 2022Updated 3 years ago
- ☆23Mar 15, 2025Updated 11 months ago
- generate UVM testbench using python☆28Mar 24, 2018Updated 7 years ago
- uvm auto generator☆24Aug 27, 2018Updated 7 years ago
- ☆11May 31, 2016Updated 9 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆37Jan 21, 2015Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 9 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Port of the LLVM compiler infrastructure to the time-predictable processor Patmos☆15Apr 2, 2025Updated 10 months ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- AMBA 3 AHB UVM TB☆35Mar 21, 2019Updated 6 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- ☆10Aug 12, 2021Updated 4 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆83Oct 2, 2019Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆100Jan 27, 2024Updated 2 years ago
- ☆38Jun 3, 2024Updated last year
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Jun 19, 2020Updated 5 years ago
- ☆11Sep 26, 2023Updated 2 years ago