zhouzaixin / arm_socLinks
☆14Updated 6 years ago
Alternatives and similar repositories for arm_soc
Users that are interested in arm_soc are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Implementation of the PCIe physical layer☆48Updated last month
- ☆17Updated 10 years ago
- ☆26Updated 4 years ago
- ☆12Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- ☆36Updated 10 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- AXI Interconnect☆52Updated 4 years ago
- ☆20Updated 2 years ago
- 异步FIFO的内部实现☆24Updated 7 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- UVM examples☆11Updated 10 years ago
- Verification IP for APB protocol☆69Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- General Purpose I/O agent written in UVM☆17Updated 8 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Updated 7 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- UVM Clock and Reset Agent☆13Updated 8 years ago
- soc integration script and integration smoke script☆23Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆29Updated 5 years ago