Alternatives and similar repositories for arm_soc:

Users that are interested in arm_soc are comparing it to the libraries listed below

• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆24Updated 7 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆24Updated 8 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• jinz2014 / UVM
  UVM examples
  ☆10Updated 9 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆15Updated 3 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆14Updated 2 years ago
• imokanj / gpio_agent
  General Purpose I/O agent written in UVM
  ☆15Updated 7 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 11 months ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆26Updated 4 years ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆15Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆62Updated 4 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆19Updated 5 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 6 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆22Updated 2 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago