liyu-ao / PE-array-for-LeNet-accelerator-based-on-FPGA
This is a 4*5 PE array for LeNet accelerator based on FPGA.
☆11Updated 2 years ago
Alternatives and similar repositories for PE-array-for-LeNet-accelerator-based-on-FPGA:
Users that are interested in PE-array-for-LeNet-accelerator-based-on-FPGA are comparing it to the libraries listed below
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 9 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 3 years ago
- ☆63Updated 6 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆49Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆23Updated 3 years ago
- ☆28Updated 4 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆28Updated 4 years ago
- IC implementation of TPU☆114Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆40Updated 6 months ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆15Updated 2 months ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆18Updated 11 months ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆94Updated 4 years ago
- Template for project1 TPU☆18Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆91Updated 3 years ago