AES-based-on-FPGA developed by verilog.
☆22Apr 23, 2020Updated 6 years ago
Alternatives and similar repositories for AES-based-on-FPGA
Users that are interested in AES-based-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 8 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog☆12Feb 1, 2021Updated 5 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 4 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆19Dec 16, 2017Updated 8 years ago
- ☆29Feb 5, 2021Updated 5 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 13 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- AES hardware engine for Xilinx Zynq platform☆32Aug 22, 2021Updated 5 years ago
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 杭州电子科技大学 数电实验 工程文件及报告☆21Oct 22, 2025Updated last year
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Oct 19, 2026Updated 2 weeks ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆18Mar 22, 2017Updated 9 years ago
- I2S transciever implemented in Verilog HDL☆34Oct 11, 2017Updated 9 years ago
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆471Dec 29, 2025Updated 10 months ago
- Instructions for the Course Mastering Argo Rollouts: Progressive Delivery in Kubernetes☆13Nov 19, 2024Updated last year
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 6 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- 2D discrete cosine transform (DCT) of an 8x8 image in verilog HDL☆16Sep 2, 2022Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆109Sep 9, 2018Updated 8 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- AES-128 Encryption☆11Jul 17, 2014Updated 12 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆149Jul 31, 2022Updated 4 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 6 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 7 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- ☆16May 8, 2018Updated 8 years ago