AES-based-on-FPGA developed by verilog.
☆23Apr 23, 2020Updated 6 years ago
Alternatives and similar repositories for AES-based-on-FPGA
Users that are interested in AES-based-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 8 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 3 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆18Dec 16, 2017Updated 8 years ago
- ☆28Feb 5, 2021Updated 5 years ago
- AES hardware engine for Xilinx Zynq platform☆32Aug 22, 2021Updated 4 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 13 years ago
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 11 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Jun 19, 2026Updated 2 weeks ago
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula …☆17Mar 22, 2017Updated 9 years ago
- A vLLM plugin built on the FlagOS unified multi-chip backend.☆63Updated this week
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Docker image to build personal website with resume☆11Jun 8, 2026Updated 3 weeks ago
- FPGA/AES/LeNet/VGG16☆108Sep 9, 2018Updated 7 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- 2D discrete cosine transform (DCT) of an 8x8 image in verilog HDL☆16Sep 2, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- 国科大研究生课程 操作系统高级教程2023年思考题☆12Dec 24, 2023Updated 2 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆143Jul 31, 2022Updated 3 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- AES-128 Encryption☆11Jul 17, 2014Updated 11 years ago
- AES128 is a IP crypto core using modes ECB/CBC/CTR using vpi to functional verification☆18Mar 31, 2023Updated 3 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- An interface to program any congestion control protocol for an unreliable connection based protocol sent over UDP. It comes with a clean …☆12Apr 8, 2022Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- AI Cluster Observability & Troubleshooting Toolkit. Powered by SII & Infrawaves.☆36Apr 29, 2026Updated 2 months ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆15Apr 25, 2026Updated 2 months ago
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago