Alternatives and similar repositories for core_ram_tester

Users that are interested in core_ram_tester are comparing it to the libraries listed below

• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 10 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆68Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• Angelic47 / GowinDDR3_AXI4_SpinalHDL
  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
  ☆27Updated last year
• pulp-platform / axi_spi_slave
  ☆28Updated 4 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆77Updated 3 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆81Updated last year
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆36Updated last year
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆34Updated 7 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆19Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago