BalaDhinesh / Accelerating_Standard_and_Modified_AES128
Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
☆25Updated 3 years ago
Alternatives and similar repositories for Accelerating_Standard_and_Modified_AES128:
Users that are interested in Accelerating_Standard_and_Modified_AES128 are comparing it to the libraries listed below
- ☆17Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆15Updated 9 months ago
- SRAM☆21Updated 4 years ago
- ☆12Updated last month
- SoC Based on ARM Cortex-M3☆29Updated 2 weeks ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- ☆31Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated last month
- A simple DDR3 memory controller☆54Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆11Updated last month
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- Implementing Different Adder Structures in Verilog☆62Updated 5 years ago
- Complete tutorial code.☆17Updated 10 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆29Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago