BalaDhinesh / Accelerating_Standard_and_Modified_AES128Links
Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
☆27Updated 3 years ago
Alternatives and similar repositories for Accelerating_Standard_and_Modified_AES128
Users that are interested in Accelerating_Standard_and_Modified_AES128 are comparing it to the libraries listed below
Sorting:
- ☆17Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆33Updated 6 years ago
- SRAM☆22Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- General Purpose AXI Direct Memory Access☆50Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- ☆12Updated 2 months ago
- SoC Based on ARM Cortex-M3☆32Updated 2 weeks ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- ☆20Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- ☆27Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆25Updated 3 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆11Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 4 years ago