BalaDhinesh / Accelerating_Standard_and_Modified_AES128Links
Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
☆27Updated 3 years ago
Alternatives and similar repositories for Accelerating_Standard_and_Modified_AES128
Users that are interested in Accelerating_Standard_and_Modified_AES128 are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆57Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- ☆34Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- SRAM☆22Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Advanced Architecture Labs with CVA6☆66Updated last year
- ☆12Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 5 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆60Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- ☆17Updated 2 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 10 months ago