本工程使用纯verilog编写rtl代码,在FPGA上搭建神经网络LeNet-5,实现手写数字识别的功能。
☆42Nov 18, 2024Updated last year
Alternatives and similar repositories for LeNet-5-on-FPGA
Users that are interested in LeNet-5-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Zynq/FPGA实现CNN手写数字(0-9)识别☆43Dec 14, 2024Updated last year
- Intelligent Parking Lot License Plate Recognition and Management System☆10Aug 1, 2025Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated 2 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 4 years ago
- 本项目使用 STM32F103C8T6 微控制器实现 2024 年电子设计竞赛 H 题的解决方案。项目代码和相关资源已开源,供大家学习和参考☆18Jun 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- 【2023全国大学生FPGA 创新设计竞赛】全国二等奖作品:Cortex-M0智能飞机大战游戏机 开源项目☆22Jul 13, 2024Updated 2 years ago
- 2023集创赛紫光同创杯一等奖项目☆181Jan 7, 2024Updated 2 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆17Jun 24, 2026Updated last month
- An LeNet RTL implement onto FPGA☆50May 4, 2018Updated 8 years ago
- 利用ov5640摄像头采集图像,利用4.3寸RGB屏显示捕获到的数字,并将识别到的数字显示在数码管上。☆17May 10, 2020Updated 6 years ago
- The system is a FPGA-based system that can recognize object in videos.☆17Apr 29, 2025Updated last year
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22May 7, 2024Updated 2 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FPGA/AES/LeNet/VGG16☆109Sep 9, 2018Updated 7 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆169Dec 8, 2019Updated 6 years ago
- fpga跑sobel识别算法☆48Mar 15, 2021Updated 5 years ago
- FPGA图像处理-- 车牌定位,包括二值化,腐蚀,膨胀,sobel边缘检测,水平投影和垂直投影等☆60Mar 17, 2023Updated 3 years ago
- FPGA小车, 功能: 自动变速,VGA实时画面输出,目标识别,目标跟踪☆22Jun 30, 2025Updated last year
- 基于FPGA和ov5640的实时图像采集及灰度转换系统☆26Mar 5, 2024Updated 2 years ago
- Compress, Deploy and Inference YOLOv7 on low-cost MCUs☆14Oct 30, 2025Updated 9 months ago
- 基于安路开发板的bayer视频简单处理☆20Aug 8, 2024Updated 2 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆70Dec 11, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Physical Downlink Shared Channel (PDSCH) in 5G New Radio.☆12Jan 29, 2024Updated 2 years ago
- use Zybo z7-20☆17May 21, 2025Updated last year
- Sample scripts for FPGA-based AI Edge Contest 2019☆11Mar 20, 2020Updated 6 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Mar 10, 2019Updated 7 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆44Nov 27, 2022Updated 3 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆287Apr 1, 2024Updated 2 years ago
- SNN on FPGA☆13Apr 26, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository provides several functions to generate and process race track maps containing specific local information, which is furthe…☆13Dec 2, 2021Updated 4 years ago
- ov5640_sdram_vga_FPGA☆10Mar 27, 2023Updated 3 years ago
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器,本设计基于KV260板卡,MpSoC架构均可移植☆22Dec 13, 2024Updated last year
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- Design and implementation of a video decoder on an Altera Cyclone V FPGA board.☆24Jun 6, 2026Updated 2 months ago
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆25Jul 15, 2022Updated 4 years ago
- MSPM0L1306相关项目(24电赛H题,23电赛云台)☆16Aug 4, 2024Updated 2 years ago