Alternatives and similar repositories for forastero:

Users that are interested in forastero are comparing it to the libraries listed below

• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated 2 weeks ago
• antmicro / verilator-verification-features-tests
  ☆18Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆56Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• blockwork-eda / blockwork
  An opinionated build environment for EDA projects
  ☆16Updated this week
• wallento / cocotbext-wishbone
  ☆13Updated 2 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 9 months ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 7 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆24Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆76Updated this week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆62Updated 4 months ago
• pulp-platform / svase
  ☆31Updated last month
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆56Updated this week
• schang412 / cocotbext-spi
  ☆20Updated 4 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated last month
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆23Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated this week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated 5 months ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆55Updated 2 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 2 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆109Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆49Updated 4 years ago