Intuity / forastero
Making cocotb testbenches that bit easier
☆29Updated last month
Alternatives and similar repositories for forastero
Users that are interested in forastero are comparing it to the libraries listed below
Sorting:
- SystemVerilog Linter based on pyslang☆30Updated last week
- Python interface for cross-calling with HDL☆32Updated 2 months ago
- An opinionated build environment for EDA projects☆17Updated 3 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 8 months ago
- ☆31Updated last year
- ☆31Updated 4 months ago
- Doxygen with verilog support☆37Updated 6 years ago
- ☆21Updated last month
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated last week
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆51Updated 2 weeks ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated 2 months ago
- ☆13Updated 5 months ago
- UART models for cocotb☆28Updated 2 years ago
- ☆41Updated 3 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 9 months ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- An open-source HDL register code generator fast enough to run in real time.☆64Updated last week
- Generates a SystemVerilog assertion interface for a given SV RTL design☆16Updated last month
- Characterizer☆22Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆59Updated 3 weeks ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 11 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- SystemVerilog frontend for Yosys☆103Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 3 months ago