Intuity / forastero
Making cocotb testbenches that bit easier
☆24Updated last week
Related projects ⓘ
Alternatives and complementary repositories for forastero
- Python interface for cross-calling with HDL☆23Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆53Updated 4 months ago
- SystemVerilog Linter based on pyslang☆23Updated 8 months ago
- An open-source HDL register code generator fast enough to run in real time.☆36Updated this week
- ☆13Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- ☆14Updated this week
- An opinionated build environment for EDA projects☆15Updated this week
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆22Updated last year
- ☆20Updated 2 weeks ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆21Updated last month
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- UART models for cocotb☆23Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆62Updated last year
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- YosysHQ SVA AXI Properties