Making cocotb testbenches that bit easier
☆37Updated this week
Alternatives and similar repositories for forastero
Users that are interested in forastero are comparing it to the libraries listed below
Sorting:
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 7 months ago
- Python interface for cross-calling with HDL☆47Jan 23, 2026Updated last month
- SpiceBind – spice inside HDL simulator☆56Jun 30, 2025Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆34Apr 13, 2023Updated 2 years ago
- SystemVerilog file list pruner☆16Feb 18, 2026Updated last week
- Debug waveforms with GDB☆28Nov 12, 2025Updated 3 months ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 3 months ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated 3 weeks ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Hardware transactions library for Amaranth☆22Feb 6, 2026Updated 3 weeks ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- A Python package for creating and solving constrained randomization problems.☆17Oct 14, 2024Updated last year
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31May 5, 2025Updated 9 months ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Unit testing for cocotb☆166Dec 6, 2025Updated 2 months ago
- ☆17Jun 5, 2024Updated last year
- Coverview☆28Jan 29, 2026Updated last month
- Filelist generator☆20Feb 3, 2026Updated 3 weeks ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆64Aug 18, 2021Updated 4 years ago
- A framework for FPGA emulation of mixed-signal systems☆39Jul 28, 2021Updated 4 years ago
- The UVM written in Python☆502Updated this week
- Fabric generator and CAD tools graphical frontend☆17Aug 5, 2025Updated 6 months ago
- Cocotb AHB Extension - AHB VIP☆21Dec 12, 2025Updated 2 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆135Updated this week
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Aug 26, 2024Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆78Jul 21, 2025Updated 7 months ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Feb 11, 2024Updated 2 years ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆50Feb 19, 2026Updated last week
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 2 weeks ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆120Oct 3, 2025Updated 4 months ago
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated 8 months ago
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 7 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago