Alternatives and similar repositories for forastero:

Users that are interested in forastero are comparing it to the libraries listed below

• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated 2 weeks ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆25Updated 3 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆40Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• wallento / cocotbext-wishbone
  ☆13Updated last month
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 8 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆69Updated last week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated last year
• schang412 / cocotbext-spi
  ☆20Updated 2 months ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆18Updated 2 months ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 4 months ago
• pulp-platform / svase
  ☆31Updated 3 weeks ago
• blockwork-eda / blockwork
  An opinionated build environment for EDA projects
  ☆15Updated this week
• asyncvlsi / summer2022
  Summer School Week 1 & 2 repo
  ☆11Updated 2 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆46Updated this week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆54Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆24Updated 8 months ago
• snishizawa / libretto
  Characterizer
  ☆21Updated 5 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆21Updated 2 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 6 months ago