Making cocotb testbenches that bit easier
☆40Feb 28, 2026Updated 4 months ago
Alternatives and similar repositories for forastero
Users that are interested in forastero are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Packed data structure specifications for multi-language hardware projects.☆17Jun 29, 2026Updated 3 weeks ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year
- Python interface for cross-calling with HDL☆50Mar 14, 2026Updated 4 months ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Jun 7, 2026Updated last month
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- RTLMeter benchmark suite☆31Jul 10, 2026Updated last week
- A Python package for creating and solving constrained randomization problems.☆19Jul 14, 2026Updated last week
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Digital Design Equivalence Checking☆78Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Jun 5, 2024Updated 2 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- A high throughput FFT implementation☆20Jan 17, 2022Updated 4 years ago
- APyTypes - Algorithmic data types for Python☆43Jul 13, 2026Updated last week
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 8 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆78Updated this week
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆17Feb 3, 2026Updated 5 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Unit testing for cocotb☆173Apr 18, 2026Updated 3 months ago
- Netlist API (and more) for EDA flow development☆149Updated this week
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆34Feb 2, 2026Updated 5 months ago
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 8 years ago
- SystemVerilog (IEEE 1800-2017) Simulator☆61Updated this week
- The UVM written in Python☆560Updated this week
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 4 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A hardware component library developed with ROHD.☆115Jul 1, 2026Updated 2 weeks ago
- SystemVerilog design elaborator into word-level netlist form☆238Updated this week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆68Aug 18, 2021Updated 4 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆35Oct 15, 2024Updated last year
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Apr 10, 2026Updated 3 months ago
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 9 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago