Alternatives and similar repositories for pyxsi:

Users that are interested in pyxsi are comparing it to the libraries listed below

• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆36Updated 2 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆60Updated this week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆55Updated 4 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆54Updated 2 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated last week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆27Updated 2 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 2 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆53Updated 2 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 4 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆50Updated 7 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated 2 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 11 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆63Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 8 months ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 3 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆26Updated 10 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆37Updated 3 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 2 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated 2 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago