wyvernSemi / mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
☆22Updated 3 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for mem_model
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆42Updated 11 months ago
- YosysHQ SVA AXI Properties☆31Updated last year
- UART -> AXI Bridge☆55Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- ☆13Updated last month
- SystemVerilog Linter based on pyslang☆23Updated 7 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- ☆20Updated last week
- Platform Level Interrupt Controller☆35Updated 6 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Python Tool for UVM Testbench Generation☆49Updated 5 months ago
- A compact, configurable RISC-V core☆11Updated 3 months ago
- Making cocotb testbenches that bit easier☆24Updated this week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 4 months ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆16Updated last year
- UART models for cocotb☆23Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 6 months ago
- IEEE P1735 decryptor for VHDL☆25Updated 9 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- ☆10Updated 3 months ago
- ☆26Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- ☆39Updated 2 years ago
- A simple DDR3 memory controller☆51Updated last year
- An example Python-based MDV testbench for apbi2c core☆30Updated 3 months ago