Alternatives and similar repositories for mem_model

Users that are interested in mem_model are comparing it to the libraries listed below

• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 4 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated last week
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆42Updated last year
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated last week
• schang412 / cocotbext-spi
  ☆24Updated 5 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆54Updated 2 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆65Updated last month
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆57Updated 3 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• pulp-platform / axi_llc
  ☆29Updated 3 weeks ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated last week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆14Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated 3 weeks ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 6 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 10 months ago
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago