High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
☆34Feb 2, 2026Updated 5 months ago
Alternatives and similar repositories for mem_model
Users that are interested in mem_model are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆76Feb 12, 2026Updated 5 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆35Oct 15, 2024Updated last year
- Open source ISS and logic RISC-V 32 bit project☆62Jan 20, 2026Updated 6 months ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆31Dec 5, 2024Updated last year
- ☆10Nov 2, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆148Jun 16, 2026Updated last month
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆96Updated this week
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆21Jun 14, 2026Updated last month
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆82Jun 24, 2026Updated last month
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆19Nov 11, 2025Updated 8 months ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- ☆15May 24, 2025Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆91Jul 6, 2026Updated 2 weeks ago
- Digital logic benchmark suite☆73Updated this week
- UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.☆11Dec 9, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 🌊 Tool for RTL waveform (VCD/FST) inspection via CLI☆39Updated this week
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- ☆22Sep 26, 2025Updated 9 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- ESnet general-purpose FPGA design library.☆14Jun 24, 2026Updated 3 weeks ago
- PCI Express controller model☆78Oct 5, 2022Updated 3 years ago
- OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibilit…☆20Jul 13, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆46Updated this week
- Opensource DDR3 Controller☆463Jun 12, 2026Updated last month
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- YosysHQ SVA AXI Properties☆53Feb 7, 2023Updated 3 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated 2 years ago
- AI-native Chiplet design flow based on open-source EDA toolchain☆36Updated this week