siliconcompiler / logikLinks
A configurable RTL to bitstream FPGA toolchain
☆48Updated this week
Alternatives and similar repositories for logik
Users that are interested in logik are comparing it to the libraries listed below
Sorting:
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆140Updated 6 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).☆203Updated last month
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆254Updated 3 years ago
- FPGA 101 lessons/labs☆394Updated last year
- Communication framework for RTL simulation and emulation.☆301Updated this week
- VRoom! RISC-V CPU☆511Updated last year
- SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.☆468Updated last week
- RTL logic synthesis☆115Updated 2 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆430Updated last week
- CoreScore☆166Updated last week
- FOSS Flow For FPGA☆411Updated 9 months ago
- VHDL synthesis (based on ghdl)☆349Updated 3 weeks ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- Silicon Layout Wizard☆185Updated last month
- Example LED blinking project for your FPGA dev board of choice☆185Updated 2 weeks ago
- Small footprint and configurable Ethernet core☆265Updated 2 weeks ago
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆45Updated last year
- A computer for human beings.☆47Updated 11 months ago
- List of FPGA Lattice boards using open tools☆334Updated 4 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆449Updated last year
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆679Updated 2 weeks ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆173Updated 2 years ago
- An attempt to recreate the RP2040 PIO in an FPGA☆305Updated last year
- Small footprint and configurable DRAM core☆445Updated 2 weeks ago
- Universal Memory Interface (UMI)☆153Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated last week
- Playground for VGA projects on Tiny Tapeout☆65Updated last month
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆113Updated 2 months ago