wyvernSemi / usbModel
USB virtual model in C++ for Verilog
☆29Updated 5 months ago
Alternatives and similar repositories for usbModel:
Users that are interested in usbModel are comparing it to the libraries listed below
- A padring generator for ASICs☆25Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated 3 weeks ago
- sample VCD files☆36Updated last year
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Virtual development board for HDL design☆41Updated 2 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 2 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 4 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆44Updated 2 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- ☆22Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated last month
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- An automatic clock gating utility☆46Updated 8 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆33Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- cocotb extension for nMigen☆16Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- ☆36Updated 2 years ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆18Updated 3 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago