wyvernSemi / usbModelLinks
USB virtual model in C++ for Verilog
☆32Updated last year
Alternatives and similar repositories for usbModel
Users that are interested in usbModel are comparing it to the libraries listed below
Sorting:
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆52Updated 2 weeks ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 10 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated this week
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆31Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Updated 2 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Updated last week
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- ☆33Updated 3 years ago
- Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!☆47Updated 3 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last month
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- ☆34Updated 4 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago