Universal Memory Interface (UMI)
☆167Sep 21, 2026Updated this week
Alternatives and similar repositories for umi
Users that are interested in umi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Communication framework for RTL simulation and emulation.☆322Updated this week
- Demo: how to create a custom EBRICK☆30Nov 20, 2024Updated last year
- A modular hardware abstraction library☆53Updated this week
- An open-source UCIe implementation☆128Updated this week
- ☆22Sep 26, 2025Updated 11 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆27Jul 12, 2023Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- 👾 Design ∪ Hardware☆79Updated this week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆36Dec 11, 2025Updated 9 months ago
- Modular hardware build system☆1,217Updated this week
- RISC-V Double Trap Fast-Track Extension☆15Mar 10, 2026Updated 6 months ago
- Basic Common Modules☆48Sep 3, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- UVM-SystemC reference implementation☆22Aug 26, 2026Updated 3 weeks ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆193Mar 10, 2024Updated 2 years ago
- Repository for Hornet RISC-V Core☆21Sep 15, 2022Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- RISC-V Nox core☆72Jul 22, 2025Updated last year
- A hardware component library developed with ROHD.☆115Sep 10, 2026Updated last week
- Open source ISS and logic RISC-V 32 bit project☆64Sep 1, 2026Updated 3 weeks ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Hardware Snappy decompressor☆12Sep 11, 2024Updated 2 years ago
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated last year
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆26Jun 14, 2026Updated 3 months ago
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆228Jun 5, 2026Updated 3 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆123Apr 1, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆119Sep 12, 2026Updated last week
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆35Oct 15, 2024Updated last year
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 9 months ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open-source UCIe implementation developed at UC Berkeley.☆21Jul 8, 2024Updated 2 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 10 years ago
- APB Logic☆29Sep 14, 2026Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆123Jun 18, 2026Updated 3 months ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆53Updated this week
- Open source RTL simulation acceleration on commodity hardware☆36Apr 13, 2023Updated 3 years ago