zeroasiccorp / umi
Universal Memory Interface (UMI)
☆145Updated last month
Alternatives and similar repositories for umi:
Users that are interested in umi are comparing it to the libraries listed below
- The multi-core cluster of a PULP system.☆91Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Raptor end-to-end FPGA Compiler and GUI☆78Updated 4 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 10 months ago
- Self checking RISC-V directed tests☆105Updated 2 months ago
- ☆59Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- Fabric generator and CAD tools☆179Updated 3 weeks ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- RISC-V Verification Interface☆89Updated 2 months ago
- Communication framework for RTL simulation and emulation.☆285Updated last month
- ☆92Updated last year
- A pipelined RISC-V processor☆55Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated 2 weeks ago
- FuseSoC standard core library☆134Updated last month
- Generic Register Interface (contains various adapters)☆117Updated 7 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- ☆78Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- A curated list of awesome resources for HDL design and verification☆146Updated last week
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 5 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆96Updated this week
- SystemVerilog frontend for Yosys☆103Updated this week