Universal Memory Interface (UMI)
☆159May 13, 2026Updated last week
Alternatives and similar repositories for umi
Users that are interested in umi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Communication framework for RTL simulation and emulation.☆311May 5, 2026Updated 2 weeks ago
- Demo: how to create a custom EBRICK☆26Nov 20, 2024Updated last year
- Verilog hardware abstraction library☆53May 12, 2026Updated last week
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆43Updated this week
- An open-source UCIe implementation☆103May 8, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Modular hardware build system☆1,158Updated this week
- SystemVerilog Functional Coverage for RISC-V ISA☆36Dec 11, 2025Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆76Updated this week
- Basic Common Modules☆48Apr 30, 2026Updated 3 weeks ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆189Mar 10, 2024Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 6 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 11 months ago
- Coverview☆28May 13, 2026Updated last week
- RISC-V Nox core☆72Jul 22, 2025Updated 10 months ago
- A hardware component library developed with ROHD.☆113May 3, 2026Updated 2 weeks ago
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated 4 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- Demo SoC for SiliconCompiler.☆63Mar 29, 2026Updated last month
- ☆15May 6, 2026Updated 2 weeks ago
- Repository for Hornet RISC-V Core☆20Sep 15, 2022Updated 3 years ago
- Opensource DDR3 Controller☆437Jan 18, 2026Updated 4 months ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆24Jul 12, 2023Updated 2 years ago
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆223May 11, 2026Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆121Apr 1, 2024Updated 2 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 5 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆104Apr 20, 2026Updated last month
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆39May 15, 2026Updated last week
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated last year
- APB Logic☆26Updated this week
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- ☆22Sep 26, 2025Updated 7 months ago