Alternatives and similar repositories for sdcx

Users that are interested in sdcx are comparing it to the libraries listed below

• ethanuppal / marlin
  🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆62Updated 3 weeks ago
• djg / verilated-rs
  Verilator Porcelain
  ☆48Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆21Updated 5 years ago
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆84Updated 2 weeks ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆43Updated 3 weeks ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated this week
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆141Updated 6 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆21Updated 2 years ago
• Raamakrishnan / verilog-filelist-parser
  A Verilog Filelist parser in Rust
  ☆11Updated 3 years ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 8 months ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆59Updated 2 years ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆262Updated 2 months ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆67Updated 5 months ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆17Updated last year
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated this week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆87Updated 2 weeks ago
• yupferris / kaze
  An HDL embedded in Rust.
  ☆200Updated last year
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• mattvenn / simulate-gate
  Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
  ☆14Updated last month
• taichi-ishitani / rice
  ☆17Updated 2 weeks ago
• Jacajack / hdl
  A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
  ☆22Updated 6 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆60Updated this week
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• SkyworksSolutionsInc / fplib
  Fixed point math library for SystemVerilog
  ☆35Updated 9 months ago