dalance / sdcxLinks
☆13Updated this week
Alternatives and similar repositories for sdcx
Users that are interested in sdcx are comparing it to the libraries listed below
Sorting:
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆49Updated last month
- Verilator Porcelain☆47Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Logic circuit analysis and optimization☆43Updated last week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆74Updated this week
- SystemVerilog language server client for Visual Studio Code☆21Updated 2 years ago
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated 3 weeks ago
- 21st century electronic design automation tools, written in Rust.☆30Updated this week
- ☆14Updated last year
- A new Hardware Design Language that keeps you in the driver's seat☆111Updated this week
- The LLHD reference simulator.☆39Updated 4 years ago
- Verilog parsing and generator crate.☆21Updated 5 years ago
- Verilog AST☆21Updated last year
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 6 months ago
- Verilog generation tool written in Rust☆59Updated 2 years ago
- A simple digital waveform viewer with vi-like key bindings.☆138Updated 4 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Verylup: the Veryl toolchain installer☆13Updated this week
- RISCV Core written in Calyx☆16Updated 10 months ago
- PicoRV☆44Updated 5 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- An automatic clock gating utility☆50Updated 2 months ago
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- Chisel Fixed-Point Arithmetic Library☆14Updated 6 months ago
- A hardware compiler based on LLHD and CIRCT☆261Updated 2 weeks ago
- ☆14Updated 3 months ago
- A tiny RISC-V instruction decoder and instruction set simulator☆21Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Updated last year