dalance / sdcxLinks
☆15Updated last week
Alternatives and similar repositories for sdcx
Users that are interested in sdcx are comparing it to the libraries listed below
Sorting:
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆69Updated last week
- Verilator Porcelain☆49Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A simple digital waveform viewer with vi-like key bindings.☆143Updated 7 months ago
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- Verilog generation tool written in Rust☆59Updated 2 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆96Updated last month
- The LLHD reference simulator.☆39Updated 5 years ago
- A hardware compiler based on LLHD and CIRCT☆263Updated 3 months ago
- Logic circuit analysis and optimization☆42Updated 2 months ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- SystemVerilog language server client for Visual Studio Code☆22Updated 2 years ago
- VHDL Language Support for VSCode☆68Updated 6 months ago
- An HDL embedded in Rust.☆200Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 9 months ago
- A new Hardware Design Language that keeps you in the driver's seat☆116Updated last week
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆33Updated 2 weeks ago
- A SystemVerilog language server based on the Slang library.☆47Updated last week
- Rust on the Zynq UltraScale+ MPSoC☆42Updated 6 years ago
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated 2 months ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 7 months ago
- System on Chip toolkit for Amaranth HDL☆95Updated last year
- ☆30Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆13Updated last year
- ☆20Updated last month
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- RISCV Core written in Calyx☆17Updated last year
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Updated 4 years ago