Alternatives and similar repositories for sdcx

Users that are interested in sdcx are comparing it to the libraries listed below

• ethanuppal / marlin
  🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆65Updated last month
• djg / verilated-rs
  Verilator Porcelain
  ☆49Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆42Updated last month
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆89Updated last month
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆59Updated 2 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆17Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆141Updated 6 months ago
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆21Updated 5 years ago
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆262Updated 3 months ago
• spade-lang / spade
  A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…
  ☆31Updated last week
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• yupferris / kaze
  An HDL embedded in Rust.
  ☆200Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 11 months ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang parser and library.
  ☆36Updated last week
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆21Updated 2 years ago
• stefanpie / sa-placer
  ☆16Updated last year
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆116Updated this week
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆67Updated 6 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆63Updated last week
• ekiwi / fst-reader
  Native Rust implementation of the FST waveform format from GTKWave.
  ☆13Updated last month
• Jacajack / hdl
  A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
  ☆22Updated 7 months ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated 2 weeks ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 9 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆36Updated 4 years ago