dalance / sdcxLinks
☆14Updated last week
Alternatives and similar repositories for sdcx
Users that are interested in sdcx are comparing it to the libraries listed below
Sorting:
- 🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆56Updated this week
- Verilator Porcelain☆48Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Logic circuit analysis and optimization☆43Updated last week
- Verilog parsing and generator crate.☆21Updated 5 years ago
- Verilog generation tool written in Rust☆59Updated 2 years ago
- A simple digital waveform viewer with vi-like key bindings.☆138Updated 5 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆80Updated last week
- The LLHD reference simulator.☆39Updated 4 years ago
- RISCV Core written in Calyx☆17Updated last year
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- A new Hardware Design Language that keeps you in the driver's seat☆114Updated last week
- SystemVerilog language server client for Visual Studio Code☆21Updated 2 years ago
- A hardware compiler based on LLHD and CIRCT☆263Updated last month
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- An HDL embedded in Rust.☆199Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 7 months ago
- End-to-end synthesis and P&R toolchain☆87Updated this week
- System on Chip toolkit for Amaranth HDL☆92Updated 10 months ago
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 5 months ago
- Verilog AST☆21Updated last year
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆30Updated last week
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- An automatic clock gating utility☆50Updated 4 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 5 months ago
- A Verilog Filelist parser in Rust☆11Updated 3 years ago
- VHDL Language Support for VSCode☆67Updated 4 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago