WAL enables programmable waveform analysis.
☆188Sep 22, 2026Updated 3 weeks ago
Alternatives and similar repositories for wal
Users that are interested in wal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 4 years ago
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- ☆20Apr 8, 2026Updated 6 months ago
- A Python package for creating and solving constrained randomization problems.☆19Sep 24, 2026Updated 2 weeks ago
- RTLMeter benchmark suite☆34Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- design and verification of asynchronous circuits☆52Sep 29, 2026Updated 2 weeks ago
- SystemVerilog design elaborator into word-level netlist form☆252Updated this week
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆75Sep 22, 2026Updated 3 weeks ago
- Project Peppercorn GateMate Test Cases☆19Sep 29, 2026Updated 2 weeks ago
- A fork of Yosys that integrates the CellIFT pass☆14Sep 12, 2026Updated last month
- Yosys plugin for logic locking and supply-chain security☆25Apr 5, 2025Updated last year
- Handle Fast Signal Traces (fst) in Python☆16Jun 11, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,476Sep 25, 2026Updated 2 weeks ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 7 months ago
- SystemVerilog compiler and language services☆1,163Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆146Updated this week
- ☆13Aug 22, 2022Updated 4 years ago
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆46Updated this week
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆151Aug 26, 2026Updated last month
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Netlist API (and more) for EDA flow development☆165Updated this week
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 11 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆556Sep 19, 2026Updated 3 weeks ago
- ☆20Oct 2, 2026Updated last week
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆63Oct 27, 2024Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆60Oct 8, 2026Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆124Sep 22, 2026Updated 3 weeks ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 9 months ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆48Oct 6, 2026Updated last week
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated last year
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆307Updated this week
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆150Oct 1, 2026Updated 2 weeks ago
- A tool for synthesizing Verilog programs☆124Aug 25, 2025Updated last year
- Fast Symbolic Repair of Hardware Design Code☆40Jan 20, 2025Updated last year
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆128Updated this week