ics-jku / wal
WAL enables programmable waveform analysis.
☆149Updated last month
Alternatives and similar repositories for wal:
Users that are interested in wal are comparing it to the libraries listed below
- SystemVerilog frontend for Yosys☆88Updated this week
- SystemVerilog synthesis tool☆189Updated last month
- Fabric generator and CAD tools☆170Updated this week
- A SystemVerilog source file pickler.☆56Updated 5 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆56Updated 3 months ago
- RISC-V Formal Verification Framework☆131Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆73Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆112Updated last year
- Control and status register code generator toolchain☆122Updated last month
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆150Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 10 months ago
- ☆92Updated last year
- ☆77Updated last year
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆36Updated 2 months ago
- A complete open-source design-for-testing (DFT) Solution☆147Updated 5 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- Generic Register Interface (contains various adapters)☆112Updated 6 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated 3 weeks ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆63Updated 6 months ago
- FuseSoC standard core library☆133Updated 2 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated last month
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Updated last year
- RISC-V Verification Interface☆88Updated last month
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Hardware generator debugger☆73Updated last year
- ☆31Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆165Updated 4 months ago