WAL enables programmable waveform analysis.
☆182May 31, 2026Updated last month
Alternatives and similar repositories for wal
Users that are interested in wal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- ☆21Apr 8, 2026Updated 2 months ago
- high-performance RTL simulator☆194Jun 19, 2024Updated 2 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An abstraction library for interfacing EDA tools☆774Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆135Jun 15, 2026Updated 2 weeks ago
- LEC - Logic Equivalence Checking - Formal Verification☆49Jun 28, 2026Updated last week
- RTLMeter benchmark suite☆31Jun 24, 2026Updated last week
- Fast Symbolic Repair of Hardware Design Code☆39Jan 20, 2025Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Apr 21, 2026Updated 2 months ago
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,429Updated this week
- Handle Fast Signal Traces (fst) in Python☆16Jun 11, 2025Updated last year
- A Python package for creating and solving constrained randomization problems.☆19Updated this week
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 3 months ago
- SystemVerilog compiler and language services☆1,078Jun 27, 2026Updated last week
- ☆13Aug 22, 2022Updated 3 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 3 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 5 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆149Mar 29, 2026Updated 3 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SystemVerilog frontend for Yosys☆233Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆525Jun 23, 2026Updated last week
- ☆20Jan 2, 2026Updated 6 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 7 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆60Oct 27, 2024Updated last year
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 7 months ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- Simple UVM environment for experimenting with Verilator.☆39Updated this week
- A fault-injection framework using Chisel and FIRRTL☆38Sep 17, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A tool for synthesizing Verilog programs☆116Aug 25, 2025Updated 10 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Feb 23, 2025Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆147Jun 17, 2026Updated 2 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆123Sep 20, 2023Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Communication framework for RTL simulation and emulation.☆316Jun 22, 2026Updated last week