WAL enables programmable waveform analysis.
☆166Nov 10, 2025Updated 4 months ago
Alternatives and similar repositories for wal
Users that are interested in wal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- ☆19Feb 12, 2026Updated last month
- high-performance RTL simulator☆188Jun 19, 2024Updated last year
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆112Mar 13, 2026Updated last week
- An abstraction library for interfacing EDA tools☆756Updated this week
- LEC - Logic Equivalence Checking - Formal Verification☆37Updated this week
- RTLMeter benchmark suite☆29Mar 15, 2026Updated last week
- Fast Symbolic Repair of Hardware Design Code☆34Jan 20, 2025Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 8 months ago
- SpiceBind – spice inside HDL simulator☆57Jun 30, 2025Updated 8 months ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆15Oct 15, 2025Updated 5 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,398Feb 13, 2026Updated last month
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 9 months ago
- A Python package for creating and solving constrained randomization problems.☆18Oct 14, 2024Updated last year
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated 2 weeks ago
- SystemVerilog compiler and language services☆989Updated this week
- ☆13Aug 22, 2022Updated 3 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆146Mar 17, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- SystemVerilog frontend for Yosys☆210Mar 19, 2026Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆500Updated this week
- ☆19Jan 2, 2026Updated 2 months ago
- Simple UVM environment for experimenting with Verilator.☆38Updated this week
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 4 months ago
- RISC-V Processor written in Amaranth HDL☆39Jan 21, 2022Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A tool for synthesizing Verilog programs☆112Aug 25, 2025Updated 7 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆120Apr 1, 2024Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆142Mar 16, 2026Updated last week
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- Communication framework for RTL simulation and emulation.☆309Mar 10, 2026Updated 2 weeks ago