WAL enables programmable waveform analysis.
☆177Nov 10, 2025Updated 5 months ago
Alternatives and similar repositories for wal
Users that are interested in wal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- ☆20Apr 8, 2026Updated 3 weeks ago
- high-performance RTL simulator☆191Jun 19, 2024Updated last year
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- An abstraction library for interfacing EDA tools☆765Apr 24, 2026Updated last week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆124Apr 13, 2026Updated 3 weeks ago
- LEC - Logic Equivalence Checking - Formal Verification☆39Updated this week
- RTLMeter benchmark suite☆31Updated this week
- Fast Symbolic Repair of Hardware Design Code☆36Jan 20, 2025Updated last year
- A fork of Yosys that integrates the CellIFT pass☆13Apr 21, 2026Updated 2 weeks ago
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated 10 months ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated last year
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆16Mar 26, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- Handle Fast Signal Traces (fst) in Python☆14Jun 11, 2025Updated 10 months ago
- A Python package for creating and solving constrained randomization problems.☆19Oct 14, 2024Updated last year
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last month
- SystemVerilog compiler and language services☆1,027Updated this week
- ☆13Aug 22, 2022Updated 3 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 3 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 4 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆147Mar 29, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog frontend for Yosys☆215Apr 28, 2026Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆504Apr 24, 2026Updated last week
- ☆19Jan 2, 2026Updated 4 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 5 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 6 months ago
- RISC-V Processor written in Amaranth HDL☆39Jan 21, 2022Updated 4 years ago
- Simple UVM environment for experimenting with Verilator.☆38Apr 29, 2026Updated last week
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 7 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A tool for synthesizing Verilog programs☆114Aug 25, 2025Updated 8 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆120Apr 1, 2024Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆144Apr 9, 2026Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Communication framework for RTL simulation and emulation.☆311Apr 28, 2026Updated last week