Alternatives and similar repositories for wal

Users that are interested in wal are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆196Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆227Updated 11 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆217Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆179Updated 5 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆91Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 3 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆246Updated 5 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆134Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• pieter3d / simview
  ☆91Updated 3 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆114Updated 3 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆51Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆66Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆173Updated 2 months ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆109Updated 5 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• bsc-loca / sargantana
  ☆126Updated 5 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago