Alternatives and similar repositories for wal

Users that are interested in wal are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆211Updated 6 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• pulp-platform / cheshire-ihp130-o
  ☆53Updated 6 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆198Updated last week
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆61Updated last week
• pieter3d / simview
  ☆86Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆111Updated 4 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆102Updated last month
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆118Updated 2 weeks ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆152Updated this week
• bsc-loca / sargantana
  ☆108Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated last week
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆181Updated last week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆125Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last week