Alternatives and similar repositories for wal

Users that are interested in wal are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆190Updated this week
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆211Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆161Updated last month
• pieter3d / simview
  ☆79Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆167Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 5 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆120Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆142Updated last month
• chipsalliance / uvm-verilator
  ☆96Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 3 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 3 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆65Updated 3 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 2 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 5 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆151Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month