Alternatives and similar repositories for caravel_vdp_lite

Users that are interested in caravel_vdp_lite are comparing it to the libraries listed below

• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆36Updated 2 years ago
• efabless / clear
  ☆70Updated 11 months ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• mattvenn / caravel_user_project
  Zero to ASIC group submission for MPW2
  ☆13Updated 4 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 6 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 3 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• efabless / caravel_board
  ☆36Updated 8 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆52Updated 2 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• efabless / caravel-lite
  ☆17Updated 9 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 2 weeks ago
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆148Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 3 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆48Updated last month
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆51Updated last week
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• TinyTapeout / tinytapeout-mpw7
  TinyTapeout-01 submission repo
  ☆32Updated 2 years ago