Alternatives and similar repositories for AMC

Users that are interested in AMC are comparing it to the libraries listed below

• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆23Updated 5 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆61Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated 3 weeks ago
• marlls1989 / ascend-freepdk45
  A free standard cell library for SDDS-NCL circuits
  ☆27Updated 2 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 3 weeks ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆76Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆47Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• idea-fasoc / fasoc
  ☆55Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆50Updated 2 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆88Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 9 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆37Updated last month
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆14Updated 9 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago