Alternatives and similar repositories for simview:

Users that are interested in simview are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆100Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆76Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆190Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆178Updated 4 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆56Updated 4 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆55Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 3 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆145Updated 10 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆116Updated 5 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆128Updated last week
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 5 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆103Updated 3 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆149Updated 2 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆82Updated 6 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago