☆95Oct 13, 2025Updated 5 months ago
Alternatives and similar repositories for simview
Users that are interested in simview are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆37Sep 19, 2024Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆253Feb 22, 2026Updated last month
- Convert an image to a GDS format for inclusion in a zerotoasic project☆19Jun 16, 2022Updated 3 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Apr 5, 2026Updated last week
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆35Dec 25, 2025Updated 3 months ago
- ☆20Dec 23, 2020Updated 5 years ago
- A command-line tool for displaying vcd waveforms.☆69Feb 19, 2024Updated 2 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- ☆38Dec 29, 2022Updated 3 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- SystemVerilog compiler and language services☆1,002Updated this week
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆371Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- A complete open-source design-for-testing (DFT) Solution☆185Aug 30, 2025Updated 7 months ago
- Bit streams forthe Ulx3s ECP5 device☆18Apr 9, 2023Updated 3 years ago
- Prefix tree adder space exploration library☆55Jan 27, 2026Updated 2 months ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Mar 3, 2026Updated last month
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,807Mar 13, 2026Updated 3 weeks ago
- SystemVerilog frontend for Yosys☆212Apr 2, 2026Updated last week
- An abstraction library for interfacing EDA tools☆757Apr 1, 2026Updated last week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- nMigen examples for the ULX3S board☆12May 5, 2022Updated 3 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- FOMU keystroke injector☆12Aug 7, 2023Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆144Mar 25, 2026Updated 2 weeks ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- ☆12May 20, 2021Updated 4 years ago
- Modular hardware build system☆1,142Updated this week
- RTLMeter benchmark suite☆31Mar 31, 2026Updated last week
- Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC…☆18May 19, 2021Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆156Apr 3, 2026Updated last week
- MBLANC: mini Board Lab and Companion☆11Jan 5, 2023Updated 3 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Oct 4, 2021Updated 4 years ago
- The binaries for SaxonSoc Linux and other configurations☆17Mar 23, 2023Updated 3 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- Tools based upon slang for language server purpose☆23Mar 17, 2026Updated 3 weeks ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆241Updated this week