shalan / Awesome-Sky130-IPsLinks
☆11Updated 2 years ago
Alternatives and similar repositories for Awesome-Sky130-IPs
Users that are interested in Awesome-Sky130-IPs are comparing it to the libraries listed below
Sorting:
- ☆17Updated 8 months ago
- An automatic clock gating utility☆50Updated 2 months ago
- ☆37Updated 3 years ago
- ☆48Updated 5 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆33Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Extended and external tests for Verilator testing☆16Updated this week
- Platform Level Interrupt Controller☆41Updated last year
- ☆35Updated 8 months ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Parasitic capacitance analysis of foundry metal stackups☆15Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A current mode buck converter on the SKY130 PDK☆27Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆19Updated last year
- Demo SoC for SiliconCompiler.☆59Updated last month
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- a Python framework for managing embedded HW/SW projects☆17Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆44Updated last month
- Characterizer☆28Updated last month
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago