r09g / iadcLinks
12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
☆20Updated 2 years ago
Alternatives and similar repositories for iadc
Users that are interested in iadc are comparing it to the libraries listed below
Sorting:
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆17Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆24Updated 6 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- Audio filtering with pyfda and cocotb☆12Updated 4 years ago
- ☆29Updated 4 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated 3 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆30Updated 8 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 4 years ago
- Open FPGA Modules☆24Updated 10 months ago
- A current mode buck converter on the SKY130 PDK☆29Updated 4 years ago
- Time to Digital Converter (TDC)☆31Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- Testbenches for HDL projects☆20Updated last week
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated 2 weeks ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- A library of verilog and vhdl modules☆15Updated 6 years ago