Alternatives and similar repositories for iadc

Users that are interested in iadc are comparing it to the libraries listed below

• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆27Updated 6 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆31Updated 2 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆37Updated 4 years ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆22Updated 4 years ago
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆20Updated 5 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆34Updated 4 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆55Updated 3 years ago
• rnunes2311 / SAR_ADC_12bit
  12 bit SAR ADC IP in Skywater 130 nm PDK
  ☆23Updated last year
• shalan / Awesome-Sky130-IPs
  ☆14Updated 2 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• w32agobot / SKY130_SAR-ADC
  Fully-differential asynchronous non-binary 12-bit SAR-ADC
  ☆38Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆42Updated 4 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆39Updated 4 years ago
• vsdip / avsddac_3v3_sky130_v2
  ☆17Updated 3 years ago
• mbits-mirafra / i3c_avip
  Verification IP project for I3C protocol
  ☆22Updated 10 months ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆22Updated this week
• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆30Updated 3 years ago
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆13Updated this week
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆16Updated 4 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 8 years ago
• manjushpv / Design-and-Verification-of-Nand-Flash-Memory-Controller
  - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
 - Implemented operations : …
  ☆21Updated 7 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• rbarzic / arty-cm0-designstart
  A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
  ☆12Updated 7 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago