Alternatives and similar repositories for iadc:

Users that are interested in iadc are comparing it to the libraries listed below

• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆22Updated 6 years ago
• rnunes2311 / SAR_ADC_12bit
  12 bit SAR ADC IP in Skywater 130 nm PDK
  ☆15Updated 9 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 4 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆19Updated 4 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆18Updated 4 years ago
• vsdip / avsddac_3v3_sky130_v1
  ☆12Updated 2 years ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated last year
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 3 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆14Updated last year
• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆22Updated 2 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• vsdip / vsdsram
  An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…
  ☆11Updated 4 years ago
• stineje / sky130_cds
  This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…
  ☆22Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• proppy / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆8Updated last year
• mabrains / caravel_user_project_ldo
  Completed LDO Design for Skywaters 130nm
  ☆14Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆26Updated 11 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated this week
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• vsdip / avsddac_3v3_sky130_v2
  ☆16Updated 2 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• muhammadaldacher / Analog-design-of-4-bit-current-steering-DACs
  This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…
  ☆15Updated 5 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆32Updated 3 years ago