samlittlewood / caravel_carrierLinks
Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
☆18Updated 4 years ago
Alternatives and similar repositories for caravel_carrier
Users that are interested in caravel_carrier are comparing it to the libraries listed below
Sorting:
- Convert an image to a GDS format for inclusion in a zerotoasic project☆15Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 2 months ago
- Zero to ASIC group submission for MPW2☆13Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆38Updated 3 years ago
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- ☆17Updated 11 months ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Updated 2 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- UART cocotb module☆11Updated 4 years ago
- A current mode buck converter on the SKY130 PDK☆31Updated 4 years ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- Prefix tree adder space exploration library☆56Updated 11 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆46Updated 3 years ago
- ☆38Updated 2 years ago