freecores / sc2v
SystemC to Verilog Synthesizable Subset Translator
☆9Updated last year
Alternatives and similar repositories for sc2v:
Users that are interested in sc2v are comparing it to the libraries listed below
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Various low power labs using sky130☆12Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 weeks ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 10 years ago
- My local copy of UVM-SystemC☆12Updated 11 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- ☆12Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- ☆12Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 4 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆18Updated 10 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- ☆36Updated 2 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆19Updated 4 months ago
- PCI bridge☆18Updated 10 years ago
- ☆12Updated last month
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago