freecores / sc2vLinks
SystemC to Verilog Synthesizable Subset Translator
☆10Updated 2 years ago
Alternatives and similar repositories for sc2v
Users that are interested in sc2v are comparing it to the libraries listed below
Sorting:
- My local copy of UVM-SystemC☆13Updated last year
- Various low power labs using sky130☆13Updated 4 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- SGMII☆13Updated 11 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆22Updated 11 years ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated this week
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆13Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- NoC based MPSoC☆11Updated 11 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated 4 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Hardware Division Units☆10Updated 11 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Updated 10 months ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago