freecores / sc2vLinks
SystemC to Verilog Synthesizable Subset Translator
☆12Updated 2 years ago
Alternatives and similar repositories for sc2v
Users that are interested in sc2v are comparing it to the libraries listed below
Sorting:
- Various low power labs using sky130☆13Updated 4 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Extended and external tests for Verilator testing☆16Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 11 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated 5 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆30Updated last month
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- Universal Advanced JTAG Debug Interface☆16Updated last year
- Generic AXI master stub☆19Updated 11 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 10 months ago
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- ☆15Updated 3 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Updated 7 years ago
- ☆40Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- ☆13Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago