☆20Nov 18, 2022Updated 3 years ago
Alternatives and similar repositories for AXI_DMA
Users that are interested in AXI_DMA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆12Mar 10, 2023Updated 3 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- AXI DMA 32 / 64 bits☆129Jul 17, 2014Updated 11 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆38Oct 25, 2020Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ☆29May 11, 2021Updated 5 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆19Jun 24, 2021Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆20Sep 2, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12May 8, 2022Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- ☆22Sep 26, 2025Updated 7 months ago
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- General Purpose AXI Direct Memory Access☆67May 12, 2024Updated 2 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing☆12Sep 10, 2024Updated last year
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Aug 10, 2022Updated 3 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆15Jul 5, 2019Updated 6 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆32Nov 3, 2025Updated 6 months ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 9 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- an open source uvm verification platform for e200 (riscv)☆29May 5, 2018Updated 8 years ago
- ☆35Apr 28, 2026Updated 3 weeks ago
- NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks☆20Feb 22, 2023Updated 3 years ago