zitouni / ZynqGNURadioLinks
FPGA accelerator on GNU Radio and Zynq SoC
☆14Updated 8 years ago
Alternatives and similar repositories for ZynqGNURadio
Users that are interested in ZynqGNURadio are comparing it to the libraries listed below
Sorting:
- This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.☆16Updated 9 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆41Updated 11 months ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆63Updated 3 years ago
- ☆36Updated 5 years ago
- The implementation of AD9371 on KC705☆21Updated 3 months ago
- RFSoC Spectrum Analyser Module on PYNQ.☆85Updated last year
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆19Updated last year
- development interface mil-std-1553b for system on chip☆23Updated 7 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆87Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆63Updated last year
- Computational Storage Device based on the open source project OpenSSD.☆26Updated 4 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- Python productivity for RFSoC platforms☆80Updated 2 months ago
- I2C Master Verilog module☆34Updated 3 months ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆119Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆27Updated 4 years ago
- Gaussian noise generator Verilog IP core☆32Updated 2 years ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆77Updated 5 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆54Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆51Updated 2 years ago
- IEEE 802.16 OFDM-based transceiver system☆26Updated 6 years ago
- FPGA Technology Exchange Group相关文件管理☆51Updated last week
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 4 years ago