Alternatives and similar repositories for OpenVPU:

Users that are interested in OpenVPU are comparing it to the libraries listed below

• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 4 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• yuehniu / embeddedCNN
  Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.
  ☆25Updated 6 years ago
• PSCLab-ASU / Systolic-CNN
  ☆16Updated 4 years ago
• mfarhadi / CNNIOT
  ☆45Updated 6 years ago
• Anonymous788 / YOLO_BlockCir
  ☆33Updated 6 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 7 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆50Updated 6 years ago
• microideax / Open-Dnn
  ☆28Updated 5 years ago
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆38Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆64Updated 6 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 2 years ago
• zeasa / nvdla-compiler
  ☆44Updated 5 years ago
• awai54st / LUTNet
  ☆57Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆112Updated 4 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆23Updated 3 years ago
• dhm2013724 / Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware
  At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA
  ☆31Updated 6 years ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆89Updated 6 years ago