Alternatives and similar repositories for OpenVPU

Users that are interested in OpenVPU are comparing it to the libraries listed below

• yuehniu / embeddedCNN
  Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.
  ☆25Updated 7 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆93Updated 6 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆115Updated 4 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆38Updated 4 years ago
• VVViy / VVViy.github.io
  This is Max's blog, something interesting in it.
  ☆13Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• mfarhadi / CNNIOT
  ☆48Updated 7 years ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆31Updated 6 years ago
• Anonymous788 / YOLO_BlockCir
  ☆33Updated 6 years ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆91Updated 6 years ago
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆37Updated 6 years ago
• microideax / Open-Dnn
  ☆29Updated 6 years ago
• xjtuiair-cag / XJTU-Tripler
  XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
  ☆188Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆32Updated 6 years ago
• hisrg / Neural-Network-Compression-and-Accelerator-on-Hardware
  My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …
  ☆53Updated 2 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆112Updated 8 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 4 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• hisrg / PYNQ_CNN_Accelerator_Tutorial
  中文：
  ☆103Updated 5 years ago