Alternatives and similar repositories for dac_2018:

Users that are interested in dac_2018 are comparing it to the libraries listed below

• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• Xilinx / SDSoC_Examples
  ☆83Updated 4 years ago
• Xilinx / PYNQ-DL
  Xilinx Deep Learning IP
  ☆91Updated 3 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆89Updated 6 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 7 years ago
• wady101 / Embedded-System-Design-Flow-on-Zynq
  Updated version of the XUP Workshops
  ☆18Updated 6 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆20Updated 7 years ago
• wbrueckner / cv2PYNQ-The-project-behind-the-library
  This project describes how the cv2PYNQ python library was built
  ☆20Updated 6 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆112Updated 7 years ago
• cornell-zhang / facedetect-fpga
  ☆45Updated 5 years ago
• fpgadeveloper / pynq-ncs-yolo
  YOLO object detector for Movidius Neural Compute Stick (NCS)
  ☆52Updated 7 years ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 7 years ago
• PeterOgden / ZCU104_VideoDemo
  PYNQ demo as seen at FPL 2018
  ☆21Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• xyzxinyizhang / 2018-DAC-System-Design-Contest
  ☆53Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• phdegen / object_detection_on_zynq_mpsoc
  ☆19Updated 7 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆46Updated 4 years ago
• nachiket / papaa-opencl
  OpenCL Labs for PAPAA Summer School 2016 Edition
  ☆46Updated 7 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆50Updated 6 years ago
• yuehniu / embeddedCNN
  Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.
  ☆25Updated 6 years ago
• Caiyujie007 / OpenVPU
  This is an open CNN accelerator for everyone to use
  ☆14Updated 5 years ago
• mfarhadi / CNNIOT
  ☆45Updated 6 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 5 years ago
• wutianze / dnndk-pynqz2
  First lesson for you to use DNNDK, also it can be helpful for your AI learning
  ☆70Updated last year
• valar1234 / SDAI
  An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
  ☆15Updated 8 years ago
• wbrueckner / cv2pynq
  Python package which accelerates OpenCV image filtering functions for the PYNQ framework
  ☆47Updated 6 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated last year