max2ma / shiftNet
☆14Updated 5 years ago
Alternatives and similar repositories for shiftNet:
Users that are interested in shiftNet are comparing it to the libraries listed below
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- This is a collection of works on neural networks and neural accelerators.☆40Updated 6 years ago
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Updated last year
- ☆33Updated 6 years ago
- ☆70Updated 5 years ago
- ☆23Updated 3 years ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- ☆45Updated 5 years ago
- Codes for Binary Ensemble Neural Network: More Bits per Network or More Networks per Bit?☆31Updated 5 years ago
- ☆35Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- ☆19Updated 4 years ago
- Residual Binarized Neural Network☆43Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- DAC System Design Contest 2020☆29Updated 4 years ago
- ☆19Updated last month
- ☆33Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 3 weeks ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆134Updated 5 years ago
- Static Block Floating Point Quantization for CNN☆32Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- ☆36Updated 6 years ago
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆48Updated 2 years ago
- ☆20Updated 3 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago